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Diffstat (limited to 'dev')
-rw-r--r--dev/alpha_console.cc9
-rw-r--r--dev/baddev.cc5
-rw-r--r--dev/ide_ctrl.cc11
-rw-r--r--dev/ide_disk.cc1
-rw-r--r--dev/isa_fake.cc13
-rw-r--r--dev/ns_gige.cc72
-rw-r--r--dev/ns_gige.hh13
-rw-r--r--dev/pciconfigall.cc15
-rw-r--r--dev/pcidev.cc4
-rw-r--r--dev/pcidev.hh4
-rw-r--r--dev/platform.cc1
-rw-r--r--dev/simple_disk.hh20
-rw-r--r--dev/sinic.cc54
-rw-r--r--dev/sinic.hh12
-rw-r--r--dev/sinicreg.hh40
-rw-r--r--dev/tsunami.cc2
-rw-r--r--dev/tsunami_cchip.cc66
-rw-r--r--dev/tsunami_io.cc68
-rw-r--r--dev/tsunami_pchip.cc68
-rw-r--r--dev/uart8250.cc5
20 files changed, 198 insertions, 285 deletions
diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc
index a520e7ea9..2e8bbd1dd 100644
--- a/dev/alpha_console.cc
+++ b/dev/alpha_console.cc
@@ -53,6 +53,7 @@
#include "sim/system.hh"
using namespace std;
+using namespace AlphaISA;
AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
System *s, BaseCPU *c, Platform *p,
@@ -181,10 +182,10 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
}
break;
default:
- return Machine_Check_Fault;
+ return MachineCheckFault;
}
- return No_Fault;
+ return NoFault;
}
Fault
@@ -201,7 +202,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
val = *(uint64_t *)data;
break;
default:
- return Machine_Check_Fault;
+ return MachineCheckFault;
}
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
@@ -251,7 +252,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
panic("Unknown 64bit access, %#x\n", daddr);
}
- return No_Fault;
+ return NoFault;
}
Tick
diff --git a/dev/baddev.cc b/dev/baddev.cc
index 52c538707..87d683a5d 100644
--- a/dev/baddev.cc
+++ b/dev/baddev.cc
@@ -46,6 +46,7 @@
#include "sim/system.hh"
using namespace std;
+using namespace TheISA;
BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu,
HierParams *hier, Bus *pio_bus, const string &devicename)
@@ -66,14 +67,14 @@ BadDevice::read(MemReqPtr &req, uint8_t *data)
{
panic("Device %s not imlpmented\n", devname);
- return No_Fault;
+ return NoFault;
}
Fault
BadDevice::write(MemReqPtr &req, const uint8_t *data)
{
panic("Device %s not imlpmented\n", devname);
- return No_Fault;
+ return NoFault;
}
Tick
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index 1279efc82..56682a224 100644
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -48,6 +48,7 @@
#include "sim/sim_object.hh"
using namespace std;
+using namespace TheISA;
////
// Initialization and destruction
@@ -401,7 +402,7 @@ IdeController::read(MemReqPtr &req, uint8_t *data)
parseAddr(req->paddr, offset, channel, reg_type);
if (!io_enabled)
- return No_Fault;
+ return NoFault;
switch (reg_type) {
case BMI_BLOCK:
@@ -457,7 +458,7 @@ IdeController::read(MemReqPtr &req, uint8_t *data)
DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n",
offset, req->size, *(uint32_t*)data);
- return No_Fault;
+ return NoFault;
}
Fault
@@ -472,12 +473,12 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
parseAddr(req->paddr, offset, channel, reg_type);
if (!io_enabled)
- return No_Fault;
+ return NoFault;
switch (reg_type) {
case BMI_BLOCK:
if (!bm_enabled)
- return No_Fault;
+ return NoFault;
switch (offset) {
// Bus master IDE command register
@@ -627,7 +628,7 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n",
offset, req->size, *(uint32_t*)data);
- return No_Fault;
+ return NoFault;
}
////
diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc
index 9d8bb8825..41400c590 100644
--- a/dev/ide_disk.cc
+++ b/dev/ide_disk.cc
@@ -53,6 +53,7 @@
#include "arch/isa_traits.hh"
using namespace std;
+using namespace TheISA;
IdeDisk::IdeDisk(const string &name, DiskImage *img, PhysicalMemory *phys,
int id, Tick delay)
diff --git a/dev/isa_fake.cc b/dev/isa_fake.cc
index e2802eaa9..2afebbded 100644
--- a/dev/isa_fake.cc
+++ b/dev/isa_fake.cc
@@ -45,6 +45,7 @@
#include "sim/system.hh"
using namespace std;
+using namespace TheISA;
IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu,
HierParams *hier, Bus *pio_bus, Addr size)
@@ -73,23 +74,23 @@ IsaFake::read(MemReqPtr &req, uint8_t *data)
case sizeof(uint64_t):
*(uint64_t*)data = 0xFFFFFFFFFFFFFFFFULL;
- return No_Fault;
+ return NoFault;
case sizeof(uint32_t):
*(uint32_t*)data = 0xFFFFFFFF;
- return No_Fault;
+ return NoFault;
case sizeof(uint16_t):
*(uint16_t*)data = 0xFFFF;
- return No_Fault;
+ return NoFault;
case sizeof(uint8_t):
*(uint8_t*)data = 0xFF;
- return No_Fault;
+ return NoFault;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
DPRINTFN("Isa FakeSMC ERROR: read daddr=%#x size=%d\n", daddr, req->size);
- return No_Fault;
+ return NoFault;
}
Fault
@@ -100,7 +101,7 @@ IsaFake::write(MemReqPtr &req, const uint8_t *data)
//:Addr daddr = (req->paddr & addr_mask) >> 6;
- return No_Fault;
+ return NoFault;
}
Tick
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index 9010850ab..4b08d8497 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -84,6 +84,7 @@ const char *NsDmaState[] =
using namespace std;
using namespace Net;
+using namespace TheISA;
///////////////////////////////////////////////////////////////////////
//
@@ -130,8 +131,6 @@ NSGigE::NSGigE(Params *p)
} else if (p->payload_bus)
panic("Must define a header bus if defining a payload bus");
- pioDelayWrite = p->pio_delay_write && pioInterface;
-
intrDelay = p->intr_delay;
dmaReadDelay = p->dma_read_delay;
dmaWriteDelay = p->dma_write_delay;
@@ -575,14 +574,14 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
panic("Accessing reserved register");
} else if (daddr > RESERVED && daddr <= 0x3FC) {
readConfig(daddr & 0xff, req->size, data);
- return No_Fault;
+ return NoFault;
} else if (daddr >= MIB_START && daddr <= MIB_END) {
// don't implement all the MIB's. hopefully the kernel
// doesn't actually DEPEND upon their values
// MIB are just hardware stats keepers
uint32_t &reg = *(uint32_t *) data;
reg = 0;
- return No_Fault;
+ return NoFault;
} else if (daddr > 0x3FC)
panic("Something is messed up!\n");
@@ -784,7 +783,7 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
daddr, req->size);
}
- return No_Fault;
+ return NoFault;
}
Fault
@@ -800,17 +799,10 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
panic("Accessing reserved register");
} else if (daddr > RESERVED && daddr <= 0x3FC) {
writeConfig(daddr & 0xff, req->size, data);
- return No_Fault;
+ return NoFault;
} else if (daddr > 0x3FC)
panic("Something is messed up!\n");
- if (pioDelayWrite) {
- int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
- if (cpu >= writeQueue.size())
- writeQueue.resize(cpu + 1);
- writeQueue[cpu].push_back(RegWriteData(daddr, *(uint32_t *)data));
- }
-
if (req->size == sizeof(uint32_t)) {
uint32_t reg = *(uint32_t *)data;
uint16_t rfaddr;
@@ -823,24 +815,20 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
if (reg & CR_TXD) {
txEnable = false;
} else if (reg & CR_TXE) {
- if (!pioDelayWrite) {
- txEnable = true;
+ txEnable = true;
- // the kernel is enabling the transmit machine
- if (txState == txIdle)
- txKick();
- }
+ // the kernel is enabling the transmit machine
+ if (txState == txIdle)
+ txKick();
}
if (reg & CR_RXD) {
rxEnable = false;
} else if (reg & CR_RXE) {
- if (!pioDelayWrite) {
- rxEnable = true;
+ rxEnable = true;
- if (rxState == rxIdle)
- rxKick();
- }
+ if (rxState == rxIdle)
+ rxKick();
}
if (reg & CR_TXR)
@@ -1203,7 +1191,7 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
panic("Invalid Request Size");
}
- return No_Fault;
+ return NoFault;
}
void
@@ -2948,38 +2936,9 @@ NSGigE::unserialize(Checkpoint *cp, const std::string &section)
Tick
NSGigE::cacheAccess(MemReqPtr &req)
{
- Addr daddr = req->paddr & 0xfff;
DPRINTF(EthernetPIO, "timing access to paddr=%#x (daddr=%#x)\n",
- req->paddr, daddr);
-
- if (!pioDelayWrite || !req->cmd.isWrite())
- return curTick + pioLatency;
-
- int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
- std::list<RegWriteData> &wq = writeQueue[cpu];
- if (wq.empty())
- panic("WriteQueue for cpu %d empty timing daddr=%#x", cpu, daddr);
-
- const RegWriteData &data = wq.front();
- if (data.daddr != daddr)
- panic("read mismatch on cpu %d, daddr functional=%#x timing=%#x",
- cpu, data.daddr, daddr);
-
- if (daddr == CR) {
- if ((data.value & (CR_TXD | CR_TXE)) == CR_TXE) {
- txEnable = true;
- if (txState == txIdle)
- txKick();
- }
-
- if ((data.value & (CR_RXD | CR_RXE)) == CR_RXE) {
- rxEnable = true;
- if (rxState == rxIdle)
- rxKick();
- }
- }
+ req->paddr, req->paddr & 0xfff);
- wq.pop_front();
return curTick + pioLatency;
}
@@ -3039,7 +2998,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
Param<Tick> dma_write_factor;
Param<bool> dma_no_allocate;
Param<Tick> pio_latency;
- Param<bool> pio_delay_write;
Param<Tick> intr_delay;
Param<Tick> rx_delay;
@@ -3080,7 +3038,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
INIT_PARAM(dma_no_allocate, "Should DMA reads allocate cache lines"),
INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"),
- INIT_PARAM(pio_delay_write, ""),
INIT_PARAM(intr_delay, "Interrupt Delay in microseconds"),
INIT_PARAM(rx_delay, "Receive Delay"),
@@ -3125,7 +3082,6 @@ CREATE_SIM_OBJECT(NSGigE)
params->dma_write_factor = dma_write_factor;
params->dma_no_allocate = dma_no_allocate;
params->pio_latency = pio_latency;
- params->pio_delay_write = pio_delay_write;
params->intr_delay = intr_delay;
params->rx_delay = rx_delay;
diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index ade7e32e6..cdd8e4b9e 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -170,9 +170,6 @@ class NSGigE : public PciDev
static const Addr size = sizeof(dp_regs);
protected:
- typedef std::deque<PacketPtr> pktbuf_t;
- typedef pktbuf_t::iterator pktiter_t;
-
/** device register file */
dp_regs regs;
dp_rom rom;
@@ -239,15 +236,6 @@ class NSGigE : public PciDev
uint32_t rxDescCnt;
DmaState rxDmaState;
- struct RegWriteData {
- Addr daddr;
- uint32_t value;
- RegWriteData(Addr da, uint32_t val) : daddr(da), value(val) {}
- };
-
- std::vector<std::list<RegWriteData> > writeQueue;
- bool pioDelayWrite;
-
bool extstsEnable;
/** EEPROM State Machine */
@@ -385,7 +373,6 @@ class NSGigE : public PciDev
Tick tx_delay;
Tick rx_delay;
Tick pio_latency;
- bool pio_delay_write;
bool dma_desc_free;
bool dma_data_free;
Tick dma_read_delay;
diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc
index 396e130af..d55084fa5 100644
--- a/dev/pciconfigall.cc
+++ b/dev/pciconfigall.cc
@@ -47,6 +47,7 @@
#include "sim/system.hh"
using namespace std;
+using namespace TheISA;
PciConfigAll::PciConfigAll(const string &name,
Addr a, MemoryController *mmu,
@@ -112,16 +113,16 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
switch (req->size) {
// case sizeof(uint64_t):
// *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
- // return No_Fault;
+ // return NoFault;
case sizeof(uint32_t):
*(uint32_t*)data = 0xFFFFFFFF;
- return No_Fault;
+ return NoFault;
case sizeof(uint16_t):
*(uint16_t*)data = 0xFFFF;
- return No_Fault;
+ return NoFault;
case sizeof(uint8_t):
*(uint8_t*)data = 0xFF;
- return No_Fault;
+ return NoFault;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
@@ -131,7 +132,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
case sizeof(uint16_t):
case sizeof(uint8_t):
devices[device][func]->readConfig(reg, req->size, data);
- return No_Fault;
+ return NoFault;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
@@ -140,7 +141,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
DPRINTFN("PCI Configspace ERROR: read daddr=%#x size=%d\n",
daddr, req->size);
- return No_Fault;
+ return NoFault;
}
Fault
@@ -164,7 +165,7 @@ PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
devices[device][func]->writeConfig(reg, req->size, data);
- return No_Fault;
+ return NoFault;
}
void
diff --git a/dev/pcidev.cc b/dev/pcidev.cc
index 1d9ea137d..a05ee3803 100644
--- a/dev/pcidev.cc
+++ b/dev/pcidev.cc
@@ -72,11 +72,11 @@ PciDev::PciDev(Params *p)
Fault
PciDev::read(MemReqPtr &req, uint8_t *data)
-{ return No_Fault; }
+{ return NoFault; }
Fault
PciDev::write(MemReqPtr &req, const uint8_t *data)
-{ return No_Fault; }
+{ return NoFault; }
Fault
PciDev::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
diff --git a/dev/pcidev.hh b/dev/pcidev.hh
index efc805b3f..9427463bf 100644
--- a/dev/pcidev.hh
+++ b/dev/pcidev.hh
@@ -272,7 +272,7 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data)
return readBar4(req, req->paddr - BARAddrs[4], data);
if (isBAR(req->paddr, 5))
return readBar5(req, req->paddr - BARAddrs[5], data);
- return Machine_Check_Fault;
+ return MachineCheckFault;
}
inline Fault
@@ -290,7 +290,7 @@ PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
return writeBar4(req, req->paddr - BARAddrs[4], data);
if (isBAR(req->paddr, 5))
return writeBar5(req, req->paddr - BARAddrs[5], data);
- return Machine_Check_Fault;
+ return MachineCheckFault;
}
#endif // __DEV_PCIDEV_HH__
diff --git a/dev/platform.cc b/dev/platform.cc
index 58f94db7b..5b667b12c 100644
--- a/dev/platform.cc
+++ b/dev/platform.cc
@@ -31,6 +31,7 @@
#include "sim/sim_exit.hh"
using namespace std;
+using namespace TheISA;
Platform::Platform(const string &name, IntrControl *intctrl, PciConfigAll *pci)
: SimObject(name), intrctrl(intctrl), pciconfig(pci)
diff --git a/dev/simple_disk.hh b/dev/simple_disk.hh
index 6560e15c2..57f81c5a9 100644
--- a/dev/simple_disk.hh
+++ b/dev/simple_disk.hh
@@ -44,19 +44,19 @@ class PhysicalMemory;
*/
class SimpleDisk : public SimObject
{
-public:
- typedef uint64_t baddr_t;
+ public:
+ typedef uint64_t baddr_t;
-protected:
- PhysicalMemory *physmem;
- DiskImage *image;
+ protected:
+ PhysicalMemory *physmem;
+ DiskImage *image;
-public:
- SimpleDisk(const std::string &name, PhysicalMemory *pmem, DiskImage *img);
- ~SimpleDisk();
+ public:
+ SimpleDisk(const std::string &name, PhysicalMemory *pmem, DiskImage *img);
+ ~SimpleDisk();
- void read(Addr addr, baddr_t block, int count) const;
- void write(Addr addr, baddr_t block, int count);
+ void read(Addr addr, baddr_t block, int count) const;
+ void write(Addr addr, baddr_t block, int count);
};
#endif // __DEV_SIMPLE_DISK_HH__
diff --git a/dev/sinic.cc b/dev/sinic.cc
index 69239df32..c499d2f49 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -50,6 +50,7 @@
#include "targetarch/vtophys.hh"
using namespace Net;
+using namespace TheISA;
namespace Sinic {
@@ -112,8 +113,6 @@ Device::Device(Params *p)
p->dma_no_allocate);
} else if (p->payload_bus)
panic("must define a header bus if defining a payload bus");
-
- pioDelayWrite = p->pio_delay_write && pioInterface;
}
Device::~Device()
@@ -352,9 +351,6 @@ Device::prepareRead(int cpu, int index)
void
Device::prepareWrite(int cpu, int index)
{
- if (cpu >= writeQueue.size())
- writeQueue.resize(cpu + 1);
-
prepareIO(cpu, index);
}
@@ -367,11 +363,11 @@ Device::read(MemReqPtr &req, uint8_t *data)
assert(config.command & PCI_CMD_MSE);
Fault fault = readBar(req, data);
- if (fault == Machine_Check_Fault) {
+ if (fault == MachineCheckFault) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
- return Machine_Check_Fault;
+ return MachineCheckFault;
}
return fault;
@@ -421,7 +417,7 @@ Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
if (raddr == Regs::IntrStatus)
devIntrClear();
- return No_Fault;
+ return NoFault;
}
/**
@@ -451,7 +447,7 @@ Device::iprRead(Addr daddr, int cpu, uint64_t &result)
DPRINTF(EthernetPIO, "IPR read %s: cpu=%s da=%#x val=%#x\n",
info.name, cpu, result);
- return No_Fault;
+ return NoFault;
}
/**
@@ -463,11 +459,11 @@ Device::write(MemReqPtr &req, const uint8_t *data)
assert(config.command & PCI_CMD_MSE);
Fault fault = writeBar(req, data);
- if (fault == Machine_Check_Fault) {
+ if (fault == MachineCheckFault) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
- return Machine_Check_Fault;
+ return MachineCheckFault;
}
return fault;
@@ -493,22 +489,18 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
panic("invalid size for %s: cpu=%d da=%#x pa=%#x va=%#x size=%d",
info.name, cpu, daddr, req->paddr, req->vaddr, req->size);
- uint32_t reg32 = *(uint32_t *)data;
+ //uint32_t reg32 = *(uint32_t *)data;
uint64_t reg64 = *(uint64_t *)data;
DPRINTF(EthernetPIO,
"write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n",
- info.name, cpu, info.size == 4 ? reg32 : reg64, daddr,
+ info.name, cpu, info.size == 4 ? (*(uint32_t *)data) : reg64, daddr,
req->paddr, req->vaddr, req->size);
prepareWrite(cpu, index);
- if (pioDelayWrite)
- writeQueue[cpu].push_back(RegWriteData(daddr, reg64));
+ regWrite(daddr, cpu, data);
- if (!pioDelayWrite || !info.delay_write)
- regWrite(daddr, cpu, data);
-
- return No_Fault;
+ return NoFault;
}
void
@@ -1570,27 +1562,6 @@ Device::cacheAccess(MemReqPtr &req)
DPRINTF(EthernetPIO, "timing %s to paddr=%#x bar=%d daddr=%#x\n",
req->cmd.toString(), req->paddr, bar, daddr);
- if (!pioDelayWrite || !req->cmd.isWrite())
- return curTick + pioLatency;
-
- if (bar == 0) {
- int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
- std::list<RegWriteData> &wq = writeQueue[cpu];
- if (wq.empty())
- panic("WriteQueue for cpu %d empty timing daddr=%#x", cpu, daddr);
-
- const RegWriteData &data = wq.front();
- if (data.daddr != daddr)
- panic("read mismatch on cpu %d, daddr functional=%#x timing=%#x",
- cpu, data.daddr, daddr);
-
- const Regs::Info &info = regInfo(data.daddr);
- if (info.delay_write)
- regWrite(daddr, cpu, (uint8_t *)&data.value);
-
- wq.pop_front();
- }
-
return curTick + pioLatency;
}
@@ -1648,7 +1619,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
Param<Tick> dma_write_factor;
Param<bool> dma_no_allocate;
Param<Tick> pio_latency;
- Param<bool> pio_delay_write;
Param<Tick> intr_delay;
Param<Tick> rx_delay;
@@ -1692,7 +1662,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
INIT_PARAM(dma_write_factor, "multiplier for dma writes"),
INIT_PARAM(dma_no_allocate, "Should we allocat on read in cache"),
INIT_PARAM(pio_latency, "Programmed IO latency in bus cycles"),
- INIT_PARAM(pio_delay_write, ""),
INIT_PARAM(intr_delay, "Interrupt Delay"),
INIT_PARAM(rx_delay, "Receive Delay"),
@@ -1740,7 +1709,6 @@ CREATE_SIM_OBJECT(Device)
params->dma_write_factor = dma_write_factor;
params->dma_no_allocate = dma_no_allocate;
params->pio_latency = pio_latency;
- params->pio_delay_write = pio_delay_write;
params->intr_delay = intr_delay;
params->tx_delay = tx_delay;
diff --git a/dev/sinic.hh b/dev/sinic.hh
index af2f109a4..97ebf4c30 100644
--- a/dev/sinic.hh
+++ b/dev/sinic.hh
@@ -283,17 +283,6 @@ class Device : public Base
void regWrite(Addr daddr, int cpu, const uint8_t *data);
Tick cacheAccess(MemReqPtr &req);
- protected:
- struct RegWriteData {
- Addr daddr;
- uint64_t value;
- RegWriteData(Addr da, uint64_t val) : daddr(da), value(val) {}
- };
-
- std::vector<std::list<RegWriteData> > writeQueue;
-
- bool pioDelayWrite;
-
/**
* Statistics
*/
@@ -349,7 +338,6 @@ class Device : public Base
Bus *header_bus;
Bus *payload_bus;
Tick pio_latency;
- bool pio_delay_write;
PhysicalMemory *physmem;
IntrControl *intctrl;
bool rx_filter;
diff --git a/dev/sinicreg.hh b/dev/sinicreg.hh
index b7008b4e1..fc1f4c06b 100644
--- a/dev/sinicreg.hh
+++ b/dev/sinicreg.hh
@@ -157,8 +157,6 @@ struct Info
uint8_t size;
bool read;
bool write;
- bool delay_read;
- bool delay_write;
const char *name;
};
@@ -167,33 +165,33 @@ struct Info
inline const Regs::Info&
regInfo(Addr daddr)
{
- static Regs::Info invalid = { 0, false, false, false, false, "invalid" };
+ static Regs::Info invalid = { 0, false, false, "invalid" };
static Regs::Info info [] = {
- { 4, true, true, false, false, "Config" },
- { 4, false, true, false, false, "Command" },
- { 4, true, true, false, false, "IntrStatus" },
- { 4, true, true, false, false, "IntrMask" },
- { 4, true, false, false, false, "RxMaxCopy" },
- { 4, true, false, false, false, "TxMaxCopy" },
- { 4, true, false, false, false, "RxMaxIntr" },
+ { 4, true, true, "Config" },
+ { 4, false, true, "Command" },
+ { 4, true, true, "IntrStatus" },
+ { 4, true, true, "IntrMask" },
+ { 4, true, false, "RxMaxCopy" },
+ { 4, true, false, "TxMaxCopy" },
+ { 4, true, false, "RxMaxIntr" },
invalid,
- { 4, true, false, false, false, "RxFifoSize" },
- { 4, true, false, false, false, "TxFifoSize" },
- { 4, true, false, false, false, "RxFifoMark" },
- { 4, true, false, false, false, "TxFifoMark" },
- { 8, true, true, false, true, "RxData" },
+ { 4, true, false, "RxFifoSize" },
+ { 4, true, false, "TxFifoSize" },
+ { 4, true, false, "RxFifoMark" },
+ { 4, true, false, "TxFifoMark" },
+ { 8, true, true, "RxData" },
invalid,
- { 8, true, false, false, false, "RxDone" },
+ { 8, true, false, "RxDone" },
invalid,
- { 8, true, false, false, false, "RxWait" },
+ { 8, true, false, "RxWait" },
invalid,
- { 8, true, true, false, true, "TxData" },
+ { 8, true, true, "TxData" },
invalid,
- { 8, true, false, false, false, "TxDone" },
+ { 8, true, false, "TxDone" },
invalid,
- { 8, true, false, false, false, "TxWait" },
+ { 8, true, false, "TxWait" },
invalid,
- { 8, true, false, false, false, "HwAddr" },
+ { 8, true, false, "HwAddr" },
invalid,
};
diff --git a/dev/tsunami.cc b/dev/tsunami.cc
index 760848a00..58fc7434e 100644
--- a/dev/tsunami.cc
+++ b/dev/tsunami.cc
@@ -46,6 +46,8 @@
#include "sim/system.hh"
using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
Tsunami::Tsunami(const string &name, System *s, IntrControl *ic,
PciConfigAll *pci)
diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
index 2287a2a3d..4dc4413a1 100644
--- a/dev/tsunami_cchip.cc
+++ b/dev/tsunami_cchip.cc
@@ -47,6 +47,8 @@
#include "sim/system.hh"
using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
MemoryController *mmu, HierParams *hier,
@@ -92,81 +94,81 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
if (daddr & TSDEV_CC_BDIMS)
{
*(uint64_t*)data = dim[(daddr >> 4) & 0x3F];
- return No_Fault;
+ return NoFault;
}
if (daddr & TSDEV_CC_BDIRS)
{
*(uint64_t*)data = dir[(daddr >> 4) & 0x3F];
- return No_Fault;
+ return NoFault;
}
switch(regnum) {
case TSDEV_CC_CSR:
*(uint64_t*)data = 0x0;
- return No_Fault;
+ return NoFault;
case TSDEV_CC_MTR:
panic("TSDEV_CC_MTR not implemeted\n");
- return No_Fault;
+ return NoFault;
case TSDEV_CC_MISC:
*(uint64_t*)data = (ipint << 8) & 0xF |
(itint << 4) & 0xF |
(xc->cpu_id & 0x3);
- return No_Fault;
+ return NoFault;
case TSDEV_CC_AAR0:
case TSDEV_CC_AAR1:
case TSDEV_CC_AAR2:
case TSDEV_CC_AAR3:
*(uint64_t*)data = 0;
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIM0:
*(uint64_t*)data = dim[0];
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIM1:
*(uint64_t*)data = dim[1];
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIM2:
*(uint64_t*)data = dim[2];
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIM3:
*(uint64_t*)data = dim[3];
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIR0:
*(uint64_t*)data = dir[0];
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIR1:
*(uint64_t*)data = dir[1];
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIR2:
*(uint64_t*)data = dir[2];
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIR3:
*(uint64_t*)data = dir[3];
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DRIR:
*(uint64_t*)data = drir;
- return No_Fault;
+ return NoFault;
case TSDEV_CC_PRBEN:
panic("TSDEV_CC_PRBEN not implemented\n");
- return No_Fault;
+ return NoFault;
case TSDEV_CC_IIC0:
case TSDEV_CC_IIC1:
case TSDEV_CC_IIC2:
case TSDEV_CC_IIC3:
panic("TSDEV_CC_IICx not implemented\n");
- return No_Fault;
+ return NoFault;
case TSDEV_CC_MPR0:
case TSDEV_CC_MPR1:
case TSDEV_CC_MPR2:
case TSDEV_CC_MPR3:
panic("TSDEV_CC_MPRx not implemented\n");
- return No_Fault;
+ return NoFault;
case TSDEV_CC_IPIR:
*(uint64_t*)data = ipint;
- return No_Fault;
+ return NoFault;
case TSDEV_CC_ITIR:
*(uint64_t*)data = itint;
- return No_Fault;
+ return NoFault;
default:
panic("default in cchip read reached, accessing 0x%x\n");
} // uint64_t
@@ -179,7 +181,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
*(uint32_t*)data = drir;
} else
panic("invalid access size(?) for tsunami register!\n");
- return No_Fault;
+ return NoFault;
case sizeof(uint16_t):
case sizeof(uint8_t):
default:
@@ -187,7 +189,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
}
DPRINTFN("Tsunami CChip ERROR: read regnum=%#x size=%d\n", regnum, req->size);
- return No_Fault;
+ return NoFault;
}
Fault
@@ -243,16 +245,16 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
}
}
- return No_Fault;
+ return NoFault;
}
switch(regnum) {
case TSDEV_CC_CSR:
panic("TSDEV_CC_CSR write\n");
- return No_Fault;
+ return NoFault;
case TSDEV_CC_MTR:
panic("TSDEV_CC_MTR write not implemented\n");
- return No_Fault;
+ return NoFault;
case TSDEV_CC_MISC:
uint64_t ipreq;
ipreq = (*(uint64_t*)data >> 12) & 0xF;
@@ -285,13 +287,13 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
if(!supportedWrite)
panic("TSDEV_CC_MISC write not implemented\n");
- return No_Fault;
+ return NoFault;
case TSDEV_CC_AAR0:
case TSDEV_CC_AAR1:
case TSDEV_CC_AAR2:
case TSDEV_CC_AAR3:
panic("TSDEV_CC_AARx write not implemeted\n");
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIM0:
case TSDEV_CC_DIM1:
case TSDEV_CC_DIM2:
@@ -341,7 +343,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
}
}
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIR0:
case TSDEV_CC_DIR1:
case TSDEV_CC_DIR2:
@@ -363,13 +365,13 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
panic("TSDEV_CC_MPRx write not implemented\n");
case TSDEV_CC_IPIR:
clearIPI(*(uint64_t*)data);
- return No_Fault;
+ return NoFault;
case TSDEV_CC_ITIR:
clearITI(*(uint64_t*)data);
- return No_Fault;
+ return NoFault;
case TSDEV_CC_IPIQ:
reqIPI(*(uint64_t*)data);
- return No_Fault;
+ return NoFault;
default:
panic("default in cchip read reached, accessing 0x%x\n");
}
@@ -384,7 +386,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
- return No_Fault;
+ return NoFault;
}
void
diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc
index 724a5bfb9..e66d6653b 100644
--- a/dev/tsunami_io.cc
+++ b/dev/tsunami_io.cc
@@ -50,6 +50,8 @@
#include "mem/functional/memory_control.hh"
using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
TsunamiIO::RTC::RTC(const string &name, Tsunami* t, Tick i)
: _name(name), event(t, i), addr(0)
@@ -459,38 +461,38 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
// PIC1 mask read
case TSDEV_PIC1_MASK:
*(uint8_t*)data = ~mask1;
- return No_Fault;
+ return NoFault;
case TSDEV_PIC2_MASK:
*(uint8_t*)data = ~mask2;
- return No_Fault;
+ return NoFault;
case TSDEV_PIC1_ISR:
// !!! If this is modified 64bit case needs to be too
// Pal code has to do a 64 bit physical read because there is
// no load physical byte instruction
*(uint8_t*)data = picr;
- return No_Fault;
+ return NoFault;
case TSDEV_PIC2_ISR:
// PIC2 not implemnted... just return 0
*(uint8_t*)data = 0x00;
- return No_Fault;
+ return NoFault;
case TSDEV_TMR0_DATA:
pitimer.counter0.read(data);
- return No_Fault;
+ return NoFault;
case TSDEV_TMR1_DATA:
pitimer.counter1.read(data);
- return No_Fault;
+ return NoFault;
case TSDEV_TMR2_DATA:
pitimer.counter2.read(data);
- return No_Fault;
+ return NoFault;
case TSDEV_RTC_DATA:
rtc.readData(data);
- return No_Fault;
+ return NoFault;
case TSDEV_CTRL_PORTB:
if (pitimer.counter2.outputHigh())
*data = PORTB_SPKR_HIGH;
else
*data = 0x00;
- return No_Fault;
+ return NoFault;
default:
panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
}
@@ -506,7 +508,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
// Pal code has to do a 64 bit physical read because there is
// no load physical byte instruction
*(uint64_t*)data = (uint64_t)picr;
- return No_Fault;
+ return NoFault;
default:
panic("I/O Read - invalid size - va %#x size %d\n",
req->vaddr, req->size);
@@ -518,7 +520,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
}
panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
- return No_Fault;
+ return NoFault;
}
Fault
@@ -550,63 +552,63 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
tsunami->cchip->clearDRIR(55);
DPRINTF(Tsunami, "clearing pic interrupt\n");
}
- return No_Fault;
+ return NoFault;
case TSDEV_PIC2_MASK:
mask2 = *(uint8_t*)data;
//PIC2 Not implemented to interrupt
- return No_Fault;
+ return NoFault;
case TSDEV_PIC1_ACK:
// clear the interrupt on the PIC
picr &= ~(1 << (*(uint8_t*)data & 0xF));
if (!(picr & mask1))
tsunami->cchip->clearDRIR(55);
- return No_Fault;
+ return NoFault;
case TSDEV_DMA1_CMND:
- return No_Fault;
+ return NoFault;
case TSDEV_DMA2_CMND:
- return No_Fault;
+ return NoFault;
case TSDEV_DMA1_MMASK:
- return No_Fault;
+ return NoFault;
case TSDEV_DMA2_MMASK:
- return No_Fault;
+ return NoFault;
case TSDEV_PIC2_ACK:
- return No_Fault;
+ return NoFault;
case TSDEV_DMA1_RESET:
- return No_Fault;
+ return NoFault;
case TSDEV_DMA2_RESET:
- return No_Fault;
+ return NoFault;
case TSDEV_DMA1_MODE:
mode1 = *(uint8_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_DMA2_MODE:
mode2 = *(uint8_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_DMA1_MASK:
case TSDEV_DMA2_MASK:
- return No_Fault;
+ return NoFault;
case TSDEV_TMR0_DATA:
pitimer.counter0.write(data);
- return No_Fault;
+ return NoFault;
case TSDEV_TMR1_DATA:
pitimer.counter1.write(data);
- return No_Fault;
+ return NoFault;
case TSDEV_TMR2_DATA:
pitimer.counter2.write(data);
- return No_Fault;
+ return NoFault;
case TSDEV_TMR_CTRL:
pitimer.writeControl(data);
- return No_Fault;
+ return NoFault;
case TSDEV_RTC_ADDR:
rtc.writeAddr(data);
- return No_Fault;
+ return NoFault;
case TSDEV_KBD:
- return No_Fault;
+ return NoFault;
case TSDEV_RTC_DATA:
rtc.writeData(data);
- return No_Fault;
+ return NoFault;
case TSDEV_CTRL_PORTB:
// System Control Port B not implemented
- return No_Fault;
+ return NoFault;
default:
panic("I/O Write - va%#x size %d data %#x\n", req->vaddr, req->size, (int)*data);
}
@@ -619,7 +621,7 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
}
- return No_Fault;
+ return NoFault;
}
void
diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc
index e61137170..46efc3dfe 100644
--- a/dev/tsunami_pchip.cc
+++ b/dev/tsunami_pchip.cc
@@ -47,6 +47,8 @@
#include "sim/system.hh"
using namespace std;
+//Should this be AlphaISA?
+using namespace TheISA;
TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
MemoryController *mmu, HierParams *hier,
@@ -90,60 +92,60 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
switch(daddr) {
case TSDEV_PC_WSBA0:
*(uint64_t*)data = wsba[0];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA1:
*(uint64_t*)data = wsba[1];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA2:
*(uint64_t*)data = wsba[2];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA3:
*(uint64_t*)data = wsba[3];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM0:
*(uint64_t*)data = wsm[0];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM1:
*(uint64_t*)data = wsm[1];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM2:
*(uint64_t*)data = wsm[2];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM3:
*(uint64_t*)data = wsm[3];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA0:
*(uint64_t*)data = tba[0];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA1:
*(uint64_t*)data = tba[1];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA2:
*(uint64_t*)data = tba[2];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA3:
*(uint64_t*)data = tba[3];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PCTL:
*(uint64_t*)data = pctl;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PLAT:
panic("PC_PLAT not implemented\n");
case TSDEV_PC_RES:
panic("PC_RES not implemented\n");
case TSDEV_PC_PERROR:
*(uint64_t*)data = 0x00;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PERRMASK:
*(uint64_t*)data = 0x00;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PERRSET:
panic("PC_PERRSET not implemented\n");
case TSDEV_PC_TLBIV:
panic("PC_TLBIV not implemented\n");
case TSDEV_PC_TLBIA:
*(uint64_t*)data = 0x00; // shouldn't be readable, but linux
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PMONCTL:
panic("PC_PMONCTL not implemented\n");
case TSDEV_PC_PMONCNT:
@@ -162,7 +164,7 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
}
DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size);
- return No_Fault;
+ return NoFault;
}
Fault
@@ -179,49 +181,49 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
switch(daddr) {
case TSDEV_PC_WSBA0:
wsba[0] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA1:
wsba[1] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA2:
wsba[2] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA3:
wsba[3] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM0:
wsm[0] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM1:
wsm[1] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM2:
wsm[2] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM3:
wsm[3] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA0:
tba[0] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA1:
tba[1] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA2:
tba[2] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA3:
tba[3] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PCTL:
pctl = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PLAT:
panic("PC_PLAT not implemented\n");
case TSDEV_PC_RES:
panic("PC_RES not implemented\n");
case TSDEV_PC_PERROR:
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PERRMASK:
panic("PC_PERRMASK not implemented\n");
case TSDEV_PC_PERRSET:
@@ -229,7 +231,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
case TSDEV_PC_TLBIV:
panic("PC_TLBIV not implemented\n");
case TSDEV_PC_TLBIA:
- return No_Fault; // value ignored, supposted to invalidate SG TLB
+ return NoFault; // value ignored, supposted to invalidate SG TLB
case TSDEV_PC_PMONCTL:
panic("PC_PMONCTL not implemented\n");
case TSDEV_PC_PMONCNT:
@@ -249,7 +251,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
- return No_Fault;
+ return NoFault;
}
#define DMA_ADDR_MASK ULL(0x3ffffffff)
diff --git a/dev/uart8250.cc b/dev/uart8250.cc
index 71f429069..65bccee86 100644
--- a/dev/uart8250.cc
+++ b/dev/uart8250.cc
@@ -46,6 +46,7 @@
#include "sim/builder.hh"
using namespace std;
+using namespace TheISA;
Uart8250::IntrEvent::IntrEvent(Uart8250 *u, int bit)
: Event(&mainEventQueue), uart(u)
@@ -183,7 +184,7 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
break;
}
- return No_Fault;
+ return NoFault;
}
@@ -255,7 +256,7 @@ Uart8250::write(MemReqPtr &req, const uint8_t *data)
panic("Tried to access a UART port that doesn't exist\n");
break;
}
- return No_Fault;
+ return NoFault;
}
void
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-20 05:51:41 +0000