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Diffstat (limited to 'dev')
-rw-r--r--dev/alpha_console.cc4
-rw-r--r--dev/ns_gige.cc2
-rw-r--r--dev/pcidev.hh6
-rw-r--r--dev/sinic.cc42
4 files changed, 36 insertions, 18 deletions
diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc
index 2e8bbd1dd..c8327736f 100644
--- a/dev/alpha_console.cc
+++ b/dev/alpha_console.cc
@@ -182,7 +182,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
}
break;
default:
- return MachineCheckFault;
+ return genMachineCheckFault();
}
return NoFault;
@@ -202,7 +202,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
val = *(uint64_t *)data;
break;
default:
- return MachineCheckFault;
+ return genMachineCheckFault();
}
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index 4b08d8497..d6df347bc 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -49,7 +49,7 @@
#include "sim/debug.hh"
#include "sim/host.hh"
#include "sim/stats.hh"
-#include "targetarch/vtophys.hh"
+#include "arch/vtophys.hh"
const char *NsRxStateStrings[] =
{
diff --git a/dev/pcidev.hh b/dev/pcidev.hh
index 9427463bf..bdfc6b932 100644
--- a/dev/pcidev.hh
+++ b/dev/pcidev.hh
@@ -260,6 +260,7 @@ class PciDev : public DmaDevice
inline Fault
PciDev::readBar(MemReqPtr &req, uint8_t *data)
{
+ using namespace TheISA;
if (isBAR(req->paddr, 0))
return readBar0(req, req->paddr - BARAddrs[0], data);
if (isBAR(req->paddr, 1))
@@ -272,12 +273,13 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data)
return readBar4(req, req->paddr - BARAddrs[4], data);
if (isBAR(req->paddr, 5))
return readBar5(req, req->paddr - BARAddrs[5], data);
- return MachineCheckFault;
+ return genMachineCheckFault();
}
inline Fault
PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
{
+ using namespace TheISA;
if (isBAR(req->paddr, 0))
return writeBar0(req, req->paddr - BARAddrs[0], data);
if (isBAR(req->paddr, 1))
@@ -290,7 +292,7 @@ PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
return writeBar4(req, req->paddr - BARAddrs[4], data);
if (isBAR(req->paddr, 5))
return writeBar5(req, req->paddr - BARAddrs[5], data);
- return MachineCheckFault;
+ return genMachineCheckFault();
}
#endif // __DEV_PCIDEV_HH__
diff --git a/dev/sinic.cc b/dev/sinic.cc
index a9363954b..c28ab335b 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -47,7 +47,7 @@
#include "sim/eventq.hh"
#include "sim/host.hh"
#include "sim/stats.hh"
-#include "targetarch/vtophys.hh"
+#include "arch/vtophys.hh"
using namespace Net;
using namespace TheISA;
@@ -363,11 +363,11 @@ Device::read(MemReqPtr &req, uint8_t *data)
assert(config.command & PCI_CMD_MSE);
Fault fault = readBar(req, data);
- if (fault == MachineCheckFault) {
+ if (fault->isMachineCheckFault()) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
- return MachineCheckFault;
+ return genMachineCheckFault();
}
return fault;
@@ -459,11 +459,11 @@ Device::write(MemReqPtr &req, const uint8_t *data)
assert(config.command & PCI_CMD_MSE);
Fault fault = writeBar(req, data);
- if (fault == MachineCheckFault) {
+ if (fault->isMachineCheckFault()) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
- return MachineCheckFault;
+ return genMachineCheckFault();
}
return fault;
@@ -489,17 +489,35 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
panic("invalid size for %s: cpu=%d da=%#x pa=%#x va=%#x size=%d",
info.name, cpu, daddr, req->paddr, req->vaddr, req->size);
- uint32_t reg32 = *(uint32_t *)data;
- uint64_t reg64 = *(uint64_t *)data;
- VirtualReg &vnic = virtualRegs[index];
-
+ //These are commmented out because when the DPRINTF below isn't used,
+ //these values aren't used and gcc issues a warning. With -Werror,
+ //this prevents compilation.
+ //uint32_t reg32 = *(uint32_t *)data;
+ //uint64_t reg64 = *(uint64_t *)data;
DPRINTF(EthernetPIO,
"write %s: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n",
- info.name, cpu, info.size == 4 ? reg32 : reg64, daddr,
- req->paddr, req->vaddr, req->size);
+ info.name, cpu, info.size == 4 ?
+ (*(uint32_t *)data) :
+ (*(uint32_t *)data),
+ daddr, req->paddr, req->vaddr, req->size);
prepareWrite(cpu, index);
+ regWrite(daddr, cpu, data);
+
+ return NoFault;
+}
+
+void
+Device::regWrite(Addr daddr, int cpu, const uint8_t *data)
+{
+ Addr index = daddr >> Regs::VirtualShift;
+ Addr raddr = daddr & Regs::VirtualMask;
+
+ uint32_t reg32 = *(uint32_t *)data;
+ uint64_t reg64 = *(uint64_t *)data;
+ VirtualReg &vnic = virtualRegs[index];
+
switch (raddr) {
case Regs::Config:
changeConfig(reg32);
@@ -546,8 +564,6 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
}
break;
}
-
- return NoFault;
}
void