diff options
Diffstat (limited to 'dev')
| -rw-r--r-- | dev/ide_ctrl.cc | 523 | ||||
| -rw-r--r-- | dev/ide_ctrl.hh | 257 | ||||
| -rw-r--r-- | dev/ide_disk.cc | 92 | ||||
| -rw-r--r-- | dev/ide_disk.hh | 99 | ||||
| -rw-r--r-- | dev/tsunami.cc | 2 | ||||
| -rw-r--r-- | dev/tsunami.hh | 6 |
6 files changed, 975 insertions, 4 deletions
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc new file mode 100644 index 000000000..0f53ba3e8 --- /dev/null +++ b/dev/ide_ctrl.cc @@ -0,0 +1,523 @@ +/* + * Copyright (c) 2003 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <cstddef> +#include <cstdlib> +#include <string> +#include <vector> + +#include "base/trace.hh" +#include "cpu/intr_control.hh" +#include "dev/dma.hh" +#include "dev/pcireg.h" +#include "dev/pciconfigall.hh" +#include "dev/ide_disk.hh" +#include "dev/ide_ctrl.hh" +#include "mem/bus/bus.hh" +#include "mem/bus/pio_interface.hh" +#include "mem/bus/pio_interface_impl.hh" +#include "mem/bus/dma_interface.hh" +#include "dev/tsunami.hh" +#include "mem/functional_mem/memory_control.hh" +#include "mem/functional_mem/physical_memory.hh" +#include "sim/builder.hh" +#include "sim/sim_object.hh" + +using namespace std; + +//// +// Initialization and destruction +//// + +IdeController::IdeController(const string &name, IntrControl *ic, + const vector<IdeDisk *> &new_disks, + MemoryController *mmu, PciConfigAll *cf, + PciConfigData *cd, Tsunami *t, uint32_t bus_num, + uint32_t dev_num, uint32_t func_num, + Bus *host_bus, HierParams *hier) + : PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t) +{ + // put back pointer into Tsunami + tsunami->disk_controller = this; + + // initialize the PIO interface addresses + pri_cmd_addr = 0; + pri_cmd_size = BARSize[0]; + + pri_ctrl_addr = 0; + pri_ctrl_size = BARSize[1]; + + sec_cmd_addr = 0; + sec_cmd_size = BARSize[2]; + + sec_ctrl_addr = 0; + sec_ctrl_size = BARSize[3]; + + // initialize the bus master interface (BMI) address to be configured + // via PCI + bmi_addr = 0; + bmi_size = BARSize[4]; + + // zero out all of the registers + memset(regs, 0, sizeof(regs)); + memset(pci_regs, 0, sizeof(pci_regs)); + + // setup initial values + *(uint32_t *)&pci_regs[IDETIM] = 0x80008000; // enable both channels + *(uint8_t *)®s[BMI + BMIS0] = 0x60; + *(uint8_t *)®s[BMI + BMIS1] = 0x60; + + // reset all internal variables + io_enabled = false; + bm_enabled = false; + memset(cmd_in_progress, 0, sizeof(cmd_in_progress)); + + // create the PIO and DMA interfaces + if (host_bus) { + pioInterface = newPioInterface(name, hier, host_bus, this, + &IdeController::cacheAccess); + + dmaInterface = new DMAInterface<Bus>(name + ".dma", host_bus, + host_bus, 1); + } + + // setup the disks attached to controller + memset(disks, 0, sizeof(IdeDisk *) * 4); + + if (new_disks.size() > 3) + panic("IDE controllers support a maximum of 4 devices attached!\n"); + + for (int i = 0; i < new_disks.size(); i++) { + disks[i] = new_disks[i]; + disks[i]->setController(this); + } +} + +IdeController::~IdeController() +{ + for (int i = 0; i < 4; i++) + if (disks[i]) + delete disks[i]; +} + +//// +// Bus timing and bus access functions +//// + +Tick +IdeController::cacheAccess(MemReqPtr &req) +{ + // @todo Add more accurate timing to cache access + return curTick + 1000; +} + +//// +// Read and write handling +//// + +void +IdeController::ReadConfig(int offset, int size, uint8_t *data) +{ + Addr origOffset = offset; + + if (offset < PCI_DEVICE_SPECIFIC) { + PciDev::ReadConfig(offset, size, data); + } else { + if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) { + offset -= PCI_IDE_TIMING; + offset += IDETIM; + + if ((offset + size) > (IDETIM + 4)) + panic("PCI read of IDETIM with invalid size\n"); + } else if (offset == PCI_SLAVE_TIMING) { + offset -= PCI_SLAVE_TIMING; + offset += SIDETIM; + + if ((offset + size) > (SIDETIM + 1)) + panic("PCI read of SIDETIM with invalid size\n"); + } else if (offset == PCI_UDMA33_CTRL) { + offset -= PCI_UDMA33_CTRL; + offset += UDMACTL; + + if ((offset + size) > (UDMACTL + 1)) + panic("PCI read of UDMACTL with invalid size\n"); + } else if (offset >= PCI_UDMA33_TIMING && + offset < (PCI_UDMA33_TIMING + 2)) { + offset -= PCI_UDMA33_TIMING; + offset += UDMATIM; + + if ((offset + size) > (UDMATIM + 2)) + panic("PCI read of UDMATIM with invalid size\n"); + } else { + panic("PCI read of unimplemented register: %x\n", offset); + } + + memcpy((void *)data, (void *)&pci_regs[offset], size); + } + + DPRINTF(IdeCtrl, "IDE PCI read offset: %#x (%#x) size: %#x data: %#x\n", + origOffset, offset, size, *(uint32_t *)data); +} + +void +IdeController::WriteConfig(int offset, int size, uint32_t data) +{ + DPRINTF(IdeCtrl, "IDE PCI write offset: %#x size: %#x data: %#x\n", + offset, size, data); + + // do standard write stuff if in standard PCI space + if (offset < PCI_DEVICE_SPECIFIC) { + PciDev::WriteConfig(offset, size, data); + } else { + if (offset >= PCI_IDE_TIMING && offset < (PCI_IDE_TIMING + 4)) { + offset -= PCI_IDE_TIMING; + offset += IDETIM; + + if ((offset + size) > (IDETIM + 4)) + panic("PCI write to IDETIM with invalid size\n"); + } else if (offset == PCI_SLAVE_TIMING) { + offset -= PCI_SLAVE_TIMING; + offset += SIDETIM; + + if ((offset + size) > (SIDETIM + 1)) + panic("PCI write to SIDETIM with invalid size\n"); + } else if (offset == PCI_UDMA33_CTRL) { + offset -= PCI_UDMA33_CTRL; + offset += UDMACTL; + + if ((offset + size) > (UDMACTL + 1)) + panic("PCI write to UDMACTL with invalid size\n"); + } else if (offset >= PCI_UDMA33_TIMING && + offset < (PCI_UDMA33_TIMING + 2)) { + offset -= PCI_UDMA33_TIMING; + offset += UDMATIM; + + if ((offset + size) > (UDMATIM + 2)) + panic("PCI write to UDMATIM with invalid size\n"); + } else { + panic("PCI write to unimplemented register: %x\n", offset); + } + + memcpy((void *)&pci_regs[offset], (void *)&data, size); + } + + if (offset == PCI_COMMAND) { + if (config.data[offset] & IOSE) + io_enabled = true; + else + io_enabled = false; + + if (config.data[offset] & BME) + bm_enabled = true; + else + bm_enabled = false; + + } else if (data != 0xffffffff) { + switch (offset) { + case PCI0_BASE_ADDR0: + pri_cmd_addr = BARAddrs[0]; + if (pioInterface) + pioInterface->addAddrRange(pri_cmd_addr, + pri_cmd_addr + pri_cmd_size - 1); + + pri_cmd_addr = ((pri_cmd_addr | 0xf0000000000) & PA_IMPL_MASK); + break; + + case PCI0_BASE_ADDR1: + pri_ctrl_addr = BARAddrs[1]; + if (pioInterface) + pioInterface->addAddrRange(pri_ctrl_addr, + pri_ctrl_addr + pri_ctrl_size - 1); + + pri_ctrl_addr = ((pri_ctrl_addr | 0xf0000000000) & PA_IMPL_MASK); + break; + + case PCI0_BASE_ADDR2: + sec_cmd_addr = BARAddrs[2]; + if (pioInterface) + pioInterface->addAddrRange(sec_cmd_addr, + sec_cmd_addr + sec_cmd_size - 1); + + sec_cmd_addr = ((sec_cmd_addr | 0xf0000000000) & PA_IMPL_MASK); + break; + + case PCI0_BASE_ADDR3: + sec_ctrl_addr = BARAddrs[3]; + if (pioInterface) + pioInterface->addAddrRange(sec_ctrl_addr, + sec_ctrl_addr + sec_ctrl_size - 1); + + sec_ctrl_addr = ((sec_ctrl_addr | 0xf0000000000) & PA_IMPL_MASK); + break; + + case PCI0_BASE_ADDR4: + bmi_addr = BARAddrs[4]; + if (pioInterface) + pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1); + + bmi_addr = ((bmi_addr | 0xf0000000000) & PA_IMPL_MASK); + break; + } + } +} + +Fault +IdeController::read(MemReqPtr &req, uint8_t *data) +{ + Addr offset = getOffset(req->paddr); + + if (!io_enabled) + return No_Fault; + + // sanity check the size (allows byte, word, or dword access) + if (req->size != sizeof(uint8_t) && req->size != sizeof(uint16_t) && + req->size != sizeof(uint32_t)) + panic("IDE controller read of invalid size: %#x\n", req->size); + + DPRINTF(IdeCtrl, "IDE default read from offset: %#x size: %#x data: %#x\n", + offset, req->size, *(uint32_t *)®s[offset]); + + // copy the data from the control registers + memcpy((void *)data, ®s[offset], req->size); + + return No_Fault; +} + +Fault +IdeController::write(MemReqPtr &req, const uint8_t *data) +{ + int disk = 0; // selected disk index + uint8_t oldVal, newVal; + + Addr offset = getOffset(req->paddr); + + if (!io_enabled) + return No_Fault; + + if (offset >= BMI && !bm_enabled) + return No_Fault; + + switch (offset) { + // Bus master IDE command register + case (BMI + BMIC1): + case (BMI + BMIC0): + if (req->size != sizeof(uint8_t)) + panic("Invalid BMIC write size: %x\n", req->size); + + // select the current disk based on DEV bit + disk = getDisk(offset); + + oldVal = regs[offset]; + newVal = *data; + + // if a DMA transfer is in progress, R/W control cannot change + if (oldVal & SSBM) { + if ((oldVal & RWCON) ^ (newVal & RWCON)) { + (oldVal & RWCON) ? newVal |= RWCON : newVal &= ~RWCON; + } + } + + // see if the start/stop bit is being changed + if ((oldVal & SSBM) ^ (newVal & SSBM)) { + if (oldVal & SSBM) { + // stopping DMA transfer + DPRINTF(IdeCtrl, "Stopping DMA transfer\n"); + + // clear the BMIDEA bit + regs[offset + 0x2] &= ~BMIDEA; + + if (disks[disk] == NULL) + panic("DMA stop for disk %d which does not exist\n", disk); + + // inform the disk of the DMA transfer abort + disks[disk]->dmaStop(); + } else { + // starting DMA transfer + DPRINTF(IdeCtrl, "Starting DMA transfer\n"); + + // set the BMIDEA bit + regs[offset + 0x2] |= BMIDEA; + + if (disks[disk] == NULL) + panic("DMA start for disk %d which does not exist\n", + disk); + + // inform the disk of the DMA transfer start + disks[disk]->dmaStart(); + } + } + + // update the register value + regs[offset] = newVal; + break; + + // Bus master IDE status register + case (BMI + BMIS0): + case (BMI + BMIS1): + if (req->size != sizeof(uint8_t)) + panic("Invalid BMIS write size: %x\n", req->size); + + oldVal = regs[offset]; + newVal = *data; + + // the BMIDEA bit is RO + newVal |= (oldVal & BMIDEA); + + // to reset (set 0) IDEINTS and IDEDMAE, write 1 to each + if ((oldVal & IDEINTS) && (newVal & IDEINTS)) + newVal &= ~IDEINTS; // clear the interrupt? + else + (oldVal & IDEINTS) ? newVal |= IDEINTS : newVal &= ~IDEINTS; + + if ((oldVal & IDEDMAE) && (newVal & IDEDMAE)) + newVal &= ~IDEDMAE; + else + (oldVal & IDEDMAE) ? newVal |= IDEDMAE : newVal &= ~IDEDMAE; + + regs[offset] = newVal; + break; + + // Bus master IDE descriptor table pointer register + case (BMI + BMIDTP0): + case (BMI + BMIDTP1): + if (req->size != sizeof(uint32_t)) + panic("Invalid BMIDTP write size: %x\n", req->size); + + *(uint32_t *)®s[offset] = *(uint32_t *)data & ~0x3; + break; + + // Write the data word in the command register block + case (CMD1 + IDE_DATA_OFFSET): + case (CMD0 + IDE_DATA_OFFSET): + if (req->size != sizeof(uint16_t)) + panic("Invalid command block data write size: %x\n", req->size); + + break; + + // Write the command byte in command register block + case (CMD1 + IDE_COMMAND_OFFSET): + case (CMD0 + IDE_COMMAND_OFFSET): + if (req->size != sizeof(uint8_t)) + panic("Invalid command block command write size: %x\n", req->size); + + // select the disk based on the DEV bit + disk = getDisk(offset); + + if (cmd_in_progress[disk]) + panic("Command on disk %d already in progress!\n", disk); + if (disks[disk] == NULL) + panic("Specified disk %d does not exist!\n", disk); + + cmd_in_progress[disk] = true; + + // write to both the command/status and alternate status + regs[offset] = *data; + regs[offset + 3] = *data; + + // issue the command to the disk + if (disk < 2) + disks[disk]->startIO(®s[CMD0], ®s[BMI + BMIDTP0]); + else + disks[disk]->startIO(®s[CMD1], ®s[BMI + BMIDTP1]); + + break; + + default: + if (req->size != sizeof(uint8_t) && req->size != sizeof(uint16_t) && + req->size != sizeof(uint32_t)) + panic("IDE controller write of invalid write size: %x\n", + req->size); + + DPRINTF(IdeCtrl, "IDE default write offset: %#x size: %#x data: %#x\n", + offset, req->size, *(uint32_t *)data); + + // do a default copy of data into the registers + memcpy((void *)®s[offset], data, req->size); + } + + return No_Fault; +} + +//// +// Serialization +//// + +void +IdeController::serialize(std::ostream &os) +{ +} + +void +IdeController::unserialize(Checkpoint *cp, const std::string §ion) +{ +} + +#ifndef DOXYGEN_SHOULD_SKIP_THIS + +BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController) + + SimObjectParam<IntrControl *> intr_ctrl; + SimObjectVectorParam<IdeDisk *> disks; + SimObjectParam<MemoryController *> mmu; + SimObjectParam<PciConfigAll *> configspace; + SimObjectParam<PciConfigData *> configdata; + SimObjectParam<Tsunami *> tsunami; + Param<uint32_t> pci_bus; + Param<uint32_t> pci_dev; + Param<uint32_t> pci_func; + SimObjectParam<Bus *> host_bus; + SimObjectParam<HierParams *> hier; + +END_DECLARE_SIM_OBJECT_PARAMS(IdeController) + +BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController) + + INIT_PARAM(intr_ctrl, "Interrupt Controller"), + INIT_PARAM(disks, "IDE disks attached to this controller"), + INIT_PARAM(mmu, "Memory controller"), + INIT_PARAM(configspace, "PCI Configspace"), + INIT_PARAM(configdata, "PCI Config data"), + INIT_PARAM(tsunami, "Tsunami chipset pointer"), + INIT_PARAM(pci_bus, "PCI bus ID"), + INIT_PARAM(pci_dev, "PCI device number"), + INIT_PARAM(pci_func, "PCI function code"), + INIT_PARAM_DFLT(host_bus, "Host bus to attach to", NULL), + INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) + +END_INIT_SIM_OBJECT_PARAMS(IdeController) + +CREATE_SIM_OBJECT(IdeController) +{ + return new IdeController(getInstanceName(), intr_ctrl, disks, mmu, + configspace, configdata, tsunami, pci_bus, + pci_dev, pci_func, host_bus, hier); +} + +REGISTER_SIM_OBJECT("IdeController", IdeController) + +#endif //DOXYGEN_SHOULD_SKIP_THIS diff --git a/dev/ide_ctrl.hh b/dev/ide_ctrl.hh new file mode 100644 index 000000000..ac25eafe7 --- /dev/null +++ b/dev/ide_ctrl.hh @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2003 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @file + * Simple PCI IDE controller with bus mastering capability + */ + +#ifndef __IDE_CTRL_HH__ +#define __IDE_CTRL_HH__ + +#include "dev/pcidev.hh" +#include "dev/pcireg.h" +#include "dev/io_device.hh" + +#define CMD0 0x00 // Channel 0 command block offset +#define CTRL0 0x08 // Channel 0 control block offset +#define CMD1 0x0c // Channel 1 command block offset +#define CTRL1 0x14 // Channel 1 control block offset +#define BMI 0x18 // Bus master IDE offset + +#define BMIC0 0x0 // Bus master IDE command register +#define BMIS0 0x2 // Bus master IDE status register +#define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register +#define BMIC1 0x8 // Bus master IDE command register +#define BMIS1 0xa // Bus master IDE status register +#define BMIDTP1 0xc // Bus master IDE descriptor table pointer register + +// Bus master IDE command register bit fields +#define RWCON 0x08 // Bus master read/write control +#define SSBM 0x01 // Start/stop bus master + +// Bus master IDE status register bit fields +#define DMA1CAP 0x40 // Drive 1 DMA capable +#define DMA0CAP 0x20 // Drive 0 DMA capable +#define IDEINTS 0x04 // IDE Interrupt Status +#define IDEDMAE 0x02 // IDE DMA error +#define BMIDEA 0x01 // Bus master IDE active + +// IDE Command byte fields +// Taken from include/linux/ide.h +#define IDE_DATA_OFFSET (0) +#define IDE_ERROR_OFFSET (1) +#define IDE_NSECTOR_OFFSET (2) +#define IDE_SECTOR_OFFSET (3) +#define IDE_LCYL_OFFSET (4) +#define IDE_HCYL_OFFSET (5) +#define IDE_SELECT_OFFSET (6) +#define IDE_STATUS_OFFSET (7) +#define IDE_CONTROL_OFFSET (8) +#define IDE_IRQ_OFFSET (9) + +#define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET +#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET + +// PCI device specific register byte offsets +#define PCI_IDE_TIMING 0x40 +#define PCI_SLAVE_TIMING 0x44 +#define PCI_UDMA33_CTRL 0x48 +#define PCI_UDMA33_TIMING 0x4a + +#define IDETIM (0) +#define SIDETIM (4) +#define UDMACTL (5) +#define UDMATIM (6) + +// PCI Command bit fields +#define BME 0x04 // Bus master function enable +#define IOSE 0x01 // I/O space enable + +class IntrControl; +class IdeDisk; +class PciConfigAll; +class Tsunami; +class PhysicalMemory; +class BaseInterface; +class HierParams; +class Bus; + +/** + * Device model for an Intel PIIX4 IDE controller + */ + +class IdeController : public PciDev +{ + private: + /** Primary command block registers */ + Addr pri_cmd_addr; + Addr pri_cmd_size; + /** Primary control block registers */ + Addr pri_ctrl_addr; + Addr pri_ctrl_size; + /** Secondary command block registers */ + Addr sec_cmd_addr; + Addr sec_cmd_size; + /** Secondary control block registers */ + Addr sec_ctrl_addr; + Addr sec_ctrl_size; + /** Bus master interface (BMI) registers */ + Addr bmi_addr; + Addr bmi_size; + + private: + /** Registers used for programmed I/O and bus master interface */ + uint8_t regs[40]; + /** Registers used in PCI configuration */ + uint8_t pci_regs[8]; + + // Internal management variables + bool io_enabled; + bool bm_enabled; + bool cmd_in_progress[4]; + + private: + /** Pointer to the chipset */ + Tsunami *tsunami; + /** IDE disks connected to controller */ + IdeDisk *disks[4]; + + private: + /** Get offset into register file from access address */ + Addr getOffset(const Addr &addr) { + Addr offset = addr; + + if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) { + offset -= pri_cmd_addr; + offset += CMD0; + } else if (addr >= pri_ctrl_addr && + addr < (pri_ctrl_addr + pri_ctrl_size)) { + offset -= pri_ctrl_addr; + offset += CTRL0; + } else if (addr >= sec_cmd_addr && + addr < (sec_cmd_addr + sec_cmd_size)) { + offset -= sec_cmd_addr; + offset += CMD1; + } else if (addr >= sec_ctrl_addr && + addr < (sec_ctrl_addr + sec_ctrl_size)) { + offset -= sec_ctrl_addr; + offset += CTRL1; + } else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) { + offset -= bmi_addr; + offset += BMI; + } else { + panic("IDE controller access to invalid address: %#x\n", addr); + } + + return offset; + }; + /** Select the disk based on the register offset */ + int getDisk(const Addr &offset) { + int disk = 0; + + // If the offset is in the channel 1 range, disks are 2 or 3 + if (offset >= CMD1 && offset < BMI && offset >= (BMI + BMIC1)) + disk += 2; + + if (disk < 2) { + if (regs[CMD0 + IDE_STATUS_OFFSET] & 0x10) + disk += 1; + } else { + if (regs[CMD1 + IDE_STATUS_OFFSET] & 0x10) + disk += 1; + } + + return disk; + }; + + public: + /** + * Constructs and initializes this controller. + * @param name The name of this controller. + * @param ic The interrupt controller. + * @param mmu The memory controller + * @param cf PCI config space + * @param cd PCI config data + * @param bus_num The PCI bus number + * @param dev_num The PCI device number + * @param func_num The PCI function number + * @param host_bus The host bus to connect to + * @param hier The hierarchy parameters + */ + IdeController(const std::string &name, IntrControl *ic, + const vector<IdeDisk *> &new_disks, + MemoryController *mmu, PciConfigAll *cf, + PciConfigData *cd, Tsunami *t, + uint32_t bus_num, uint32_t dev_num, uint32_t func_num, + Bus *host_bus, HierParams *hier); + + /** + * Deletes the connected devices. + */ + ~IdeController(); + + virtual void WriteConfig(int offset, int size, uint32_t data); + virtual void ReadConfig(int offset, int size, uint8_t *data); + + /** + * Read a done field for a given target. + * @param req Contains the address of the field to read. + * @param data Return the field read. + * @return The fault condition of the access. + */ + virtual Fault read(MemReqPtr &req, uint8_t *data); + + /** + * Write to the mmapped I/O control registers. + * @param req Contains the address to write to. + * @param data The data to write. + * @return The fault condition of the access. + */ + virtual Fault write(MemReqPtr &req, const uint8_t *data); + + /** + * Cache access timing specific to device + * @param req Memory request + */ + Tick cacheAccess(MemReqPtr &req); + + /** + * Serialize this object to the given output stream. + * @param os The stream to serialize to. + */ + virtual void serialize(std::ostream &os); + + /** + * Reconstruct the state of this object from a checkpoint. + * @param cp The checkpoint use. + * @param section The section name of this object + */ + virtual void unserialize(Checkpoint *cp, const std::string §ion); + +}; +#endif // __IDE_CTRL_HH_ diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc new file mode 100644 index 000000000..edf01552f --- /dev/null +++ b/dev/ide_disk.cc @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2003 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @file + * Device model implementation for an IDE disk + */ + +#include <cerrno> +#include <cstring> +#include <deque> +#include <string> + +#include "base/cprintf.hh" // csprintf +#include "base/trace.hh" +#include "dev/disk_image.hh" +#include "dev/ide_disk.hh" +#include "sim/builder.hh" +#include "sim/sim_object.hh" +#include "sim/universe.hh" + +using namespace std; + +IdeDisk::IdeDisk(const string &name, DiskImage *img, int delay) + : SimObject(name), ctrl(NULL), image(img) +{ + diskDelay = delay * ticksPerSecond / 1000; +} + +IdeDisk::~IdeDisk() +{ +} + +void +IdeDisk::serialize(ostream &os) +{ +} + +void +IdeDisk::unserialize(Checkpoint *cp, const string §ion) +{ +} + +#ifndef DOXYGEN_SHOULD_SKIP_THIS + +BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeDisk) + + SimObjectParam<DiskImage *> image; + Param<int> disk_delay; + +END_DECLARE_SIM_OBJECT_PARAMS(IdeDisk) + +BEGIN_INIT_SIM_OBJECT_PARAMS(IdeDisk) + + INIT_PARAM(image, "Disk image"), + INIT_PARAM_DFLT(disk_delay, "Fixed disk delay in milliseconds", 0) + +END_INIT_SIM_OBJECT_PARAMS(IdeDisk) + + +CREATE_SIM_OBJECT(IdeDisk) +{ + return new IdeDisk(getInstanceName(), image, disk_delay); +} + +REGISTER_SIM_OBJECT("IdeDisk", IdeDisk) + +#endif //DOXYGEN_SHOULD_SKIP_THIS diff --git a/dev/ide_disk.hh b/dev/ide_disk.hh new file mode 100644 index 000000000..29ddd4be7 --- /dev/null +++ b/dev/ide_disk.hh @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2003 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/** @file + * Device model for an IDE disk + */ + +#ifndef __IDE_DISK_HH__ +#define __IDE_DISK_HH__ + +#include "dev/io_device.hh" + +class DiskImage; +class IdeController; + +/** + * SCSI Disk device model + */ +class IdeDisk : public SimObject +{ + protected: + /** The IDE controller for this disk. */ + IdeController *ctrl; + /** The image that contains the data of this disk. */ + DiskImage *image; + + protected: + /** The disk delay in milliseconds. */ + int diskDelay; + + public: + /** + * Create and initialize this Disk. + * @param name The name of this disk. + * @param img The disk image of this disk. + * @param disk_delay The disk delay in milliseconds + */ + IdeDisk(const std::string &name, DiskImage *img, int disk_delay); + + /** + * Delete the data buffer. + */ + ~IdeDisk(); + + /** + * Set the controller for this device + * @param c The IDE controller + */ + void setController(IdeController *c) { + if (ctrl) panic("Cannot change the controller once set!\n"); + ctrl = c; + } + + void startIO(uint8_t *cmdBlk, uint8_t *prdPtr) {}; + + void dmaStart() {}; + void dmaStop() {}; + + /** + * Serialize this object to the given output stream. + * @param os The stream to serialize to. + */ + void serialize(std::ostream &os); + + /** + * Reconstruct the state of this object from a checkpoint. + * @param cp The checkpoint to use. + * @param section The section name describing this object. + */ + void unserialize(Checkpoint *cp, const std::string §ion); +}; + + +#endif // __IDE_DISK_HH__ diff --git a/dev/tsunami.cc b/dev/tsunami.cc index 04ab922b9..ba33fa096 100644 --- a/dev/tsunami.cc +++ b/dev/tsunami.cc @@ -33,7 +33,7 @@ #include "cpu/intr_control.hh" #include "dev/console.hh" #include "dev/etherdev.hh" -#include "dev/adaptec_ctrl.hh" +#include "dev/ide_ctrl.hh" #include "dev/tlaser_clock.hh" #include "dev/tsunami_cchip.hh" #include "dev/tsunami_pchip.hh" diff --git a/dev/tsunami.hh b/dev/tsunami.hh index bcbd9c756..3c304dccd 100644 --- a/dev/tsunami.hh +++ b/dev/tsunami.hh @@ -37,7 +37,7 @@ #include "dev/platform.hh" -class AdaptecController; +class IdeController; class TlaserClock; class EtherDev; class TsunamiCChip; @@ -64,8 +64,8 @@ class Tsunami : public Platform System *system; /** Pointer to the TsunamiIO device which has the RTC */ TsunamiIO *io; - /** Pointer to the SCSI controller device */ - AdaptecController *scsi; + /** Pointer to the disk controller device */ + IdeController *disk_controller; /** Pointer to the ethernet controller device */ EtherDev *ethernet; |