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-rw-r--r--dev/alpha_console.cc14
-rw-r--r--dev/alpha_console.hh4
-rw-r--r--dev/baddev.cc8
-rw-r--r--dev/baddev.hh4
-rw-r--r--dev/ide_ctrl.cc14
-rw-r--r--dev/ide_ctrl.hh4
-rw-r--r--dev/isa_fake.cc16
-rw-r--r--dev/isa_fake.hh4
-rw-r--r--dev/ns_gige.cc14
-rw-r--r--dev/ns_gige.hh4
-rw-r--r--dev/pciconfigall.cc18
-rw-r--r--dev/pciconfigall.hh4
-rw-r--r--dev/pcidev.cc32
-rw-r--r--dev/pcidev.hh40
-rw-r--r--dev/sinic.cc28
-rw-r--r--dev/sinic.hh10
-rw-r--r--dev/tsunami_cchip.cc68
-rw-r--r--dev/tsunami_cchip.hh4
-rw-r--r--dev/tsunami_io.cc70
-rw-r--r--dev/tsunami_io.hh4
-rw-r--r--dev/tsunami_pchip.cc70
-rw-r--r--dev/tsunami_pchip.hh4
-rw-r--r--dev/uart.hh4
-rw-r--r--dev/uart8250.cc8
-rw-r--r--dev/uart8250.hh4
25 files changed, 227 insertions, 227 deletions
diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc
index 61b444628..38fbbdef0 100644
--- a/dev/alpha_console.cc
+++ b/dev/alpha_console.cc
@@ -99,7 +99,7 @@ AlphaConsole::startup()
alphaAccess->intrClockFrequency = platform->intrFrequency();
}
-Fault
+Fault *
AlphaConsole::read(MemReqPtr &req, uint8_t *data)
{
memset(data, 0, req->size);
@@ -183,13 +183,13 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
}
break;
default:
- return Machine_Check_Fault;
+ return MachineCheckFault;
}
- return No_Fault;
+ return NoFault;
}
-Fault
+Fault *
AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
{
uint64_t val;
@@ -203,7 +203,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
val = *(uint64_t *)data;
break;
default:
- return Machine_Check_Fault;
+ return MachineCheckFault;
}
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
@@ -256,10 +256,10 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
break;
default:
- return Machine_Check_Fault;
+ return MachineCheckFault;
}
- return No_Fault;
+ return NoFault;
}
Tick
diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh
index 74ad795f0..75f0a3a67 100644
--- a/dev/alpha_console.hh
+++ b/dev/alpha_console.hh
@@ -110,8 +110,8 @@ class AlphaConsole : public PioDevice
/**
* memory mapped reads and writes
*/
- virtual Fault read(MemReqPtr &req, uint8_t *data);
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault * read(MemReqPtr &req, uint8_t *data);
+ virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
* standard serialization routines for checkpointing
diff --git a/dev/baddev.cc b/dev/baddev.cc
index 52c538707..b6ca919e4 100644
--- a/dev/baddev.cc
+++ b/dev/baddev.cc
@@ -61,19 +61,19 @@ BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu,
}
-Fault
+Fault *
BadDevice::read(MemReqPtr &req, uint8_t *data)
{
panic("Device %s not imlpmented\n", devname);
- return No_Fault;
+ return NoFault;
}
-Fault
+Fault *
BadDevice::write(MemReqPtr &req, const uint8_t *data)
{
panic("Device %s not imlpmented\n", devname);
- return No_Fault;
+ return NoFault;
}
Tick
diff --git a/dev/baddev.hh b/dev/baddev.hh
index c2a204c05..b7b67e31a 100644
--- a/dev/baddev.hh
+++ b/dev/baddev.hh
@@ -71,7 +71,7 @@ class BadDevice : public PioDevice
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
- virtual Fault read(MemReqPtr &req, uint8_t *data);
+ virtual Fault * read(MemReqPtr &req, uint8_t *data);
/**
* On a write event we just panic aand hopefully print a
@@ -80,7 +80,7 @@ class BadDevice : public PioDevice
* @param data The data to write.
* @return The fault condition of the access.
*/
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
* Return how long this access will take.
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index 1279efc82..a5cb0dfd8 100644
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -390,7 +390,7 @@ IdeController::writeConfig(int offset, int size, const uint8_t *data)
}
}
-Fault
+Fault *
IdeController::read(MemReqPtr &req, uint8_t *data)
{
Addr offset;
@@ -401,7 +401,7 @@ IdeController::read(MemReqPtr &req, uint8_t *data)
parseAddr(req->paddr, offset, channel, reg_type);
if (!io_enabled)
- return No_Fault;
+ return NoFault;
switch (reg_type) {
case BMI_BLOCK:
@@ -457,10 +457,10 @@ IdeController::read(MemReqPtr &req, uint8_t *data)
DPRINTF(IdeCtrl, "read from offset: %#x size: %#x data: %#x\n",
offset, req->size, *(uint32_t*)data);
- return No_Fault;
+ return NoFault;
}
-Fault
+Fault *
IdeController::write(MemReqPtr &req, const uint8_t *data)
{
Addr offset;
@@ -472,12 +472,12 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
parseAddr(req->paddr, offset, channel, reg_type);
if (!io_enabled)
- return No_Fault;
+ return NoFault;
switch (reg_type) {
case BMI_BLOCK:
if (!bm_enabled)
- return No_Fault;
+ return NoFault;
switch (offset) {
// Bus master IDE command register
@@ -627,7 +627,7 @@ IdeController::write(MemReqPtr &req, const uint8_t *data)
DPRINTF(IdeCtrl, "write to offset: %#x size: %#x data: %#x\n",
offset, req->size, *(uint32_t*)data);
- return No_Fault;
+ return NoFault;
}
////
diff --git a/dev/ide_ctrl.hh b/dev/ide_ctrl.hh
index 0fbaf9207..72523f57c 100644
--- a/dev/ide_ctrl.hh
+++ b/dev/ide_ctrl.hh
@@ -213,7 +213,7 @@ class IdeController : public PciDev
* @param data Return the field read.
* @return The fault condition of the access.
*/
- virtual Fault read(MemReqPtr &req, uint8_t *data);
+ virtual Fault * read(MemReqPtr &req, uint8_t *data);
/**
* Write to the mmapped I/O control registers.
@@ -221,7 +221,7 @@ class IdeController : public PciDev
* @param data The data to write.
* @return The fault condition of the access.
*/
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
* Serialize this object to the given output stream.
diff --git a/dev/isa_fake.cc b/dev/isa_fake.cc
index e2802eaa9..93c9eedbf 100644
--- a/dev/isa_fake.cc
+++ b/dev/isa_fake.cc
@@ -59,7 +59,7 @@ IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu,
}
}
-Fault
+Fault *
IsaFake::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n",
@@ -73,26 +73,26 @@ IsaFake::read(MemReqPtr &req, uint8_t *data)
case sizeof(uint64_t):
*(uint64_t*)data = 0xFFFFFFFFFFFFFFFFULL;
- return No_Fault;
+ return NoFault;
case sizeof(uint32_t):
*(uint32_t*)data = 0xFFFFFFFF;
- return No_Fault;
+ return NoFault;
case sizeof(uint16_t):
*(uint16_t*)data = 0xFFFF;
- return No_Fault;
+ return NoFault;
case sizeof(uint8_t):
*(uint8_t*)data = 0xFF;
- return No_Fault;
+ return NoFault;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
DPRINTFN("Isa FakeSMC ERROR: read daddr=%#x size=%d\n", daddr, req->size);
- return No_Fault;
+ return NoFault;
}
-Fault
+Fault *
IsaFake::write(MemReqPtr &req, const uint8_t *data)
{
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
@@ -100,7 +100,7 @@ IsaFake::write(MemReqPtr &req, const uint8_t *data)
//:Addr daddr = (req->paddr & addr_mask) >> 6;
- return No_Fault;
+ return NoFault;
}
Tick
diff --git a/dev/isa_fake.hh b/dev/isa_fake.hh
index 290b24b54..60ca5f90a 100644
--- a/dev/isa_fake.hh
+++ b/dev/isa_fake.hh
@@ -65,14 +65,14 @@ class IsaFake : public PioDevice
* @param req The memory request.
* @param data Where to put the data.
*/
- virtual Fault read(MemReqPtr &req, uint8_t *data);
+ virtual Fault * read(MemReqPtr &req, uint8_t *data);
/**
* All writes are simply ignored.
* @param req The memory request.
* @param data the data to not write.
*/
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
* Return how long this access will take.
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index 9010850ab..c28615438 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -558,7 +558,7 @@ NSGigE::writeConfig(int offset, int size, const uint8_t* data)
* This reads the device registers, which are detailed in the NS83820
* spec sheet
*/
-Fault
+Fault *
NSGigE::read(MemReqPtr &req, uint8_t *data)
{
assert(ioEnable);
@@ -575,14 +575,14 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
panic("Accessing reserved register");
} else if (daddr > RESERVED && daddr <= 0x3FC) {
readConfig(daddr & 0xff, req->size, data);
- return No_Fault;
+ return NoFault;
} else if (daddr >= MIB_START && daddr <= MIB_END) {
// don't implement all the MIB's. hopefully the kernel
// doesn't actually DEPEND upon their values
// MIB are just hardware stats keepers
uint32_t &reg = *(uint32_t *) data;
reg = 0;
- return No_Fault;
+ return NoFault;
} else if (daddr > 0x3FC)
panic("Something is messed up!\n");
@@ -784,10 +784,10 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
daddr, req->size);
}
- return No_Fault;
+ return NoFault;
}
-Fault
+Fault *
NSGigE::write(MemReqPtr &req, const uint8_t *data)
{
assert(ioEnable);
@@ -800,7 +800,7 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
panic("Accessing reserved register");
} else if (daddr > RESERVED && daddr <= 0x3FC) {
writeConfig(daddr & 0xff, req->size, data);
- return No_Fault;
+ return NoFault;
} else if (daddr > 0x3FC)
panic("Something is messed up!\n");
@@ -1203,7 +1203,7 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
panic("Invalid Request Size");
}
- return No_Fault;
+ return NoFault;
}
void
diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index ade7e32e6..b65626b7b 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -408,8 +408,8 @@ class NSGigE : public PciDev
virtual void writeConfig(int offset, int size, const uint8_t *data);
virtual void readConfig(int offset, int size, uint8_t *data);
- virtual Fault read(MemReqPtr &req, uint8_t *data);
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault * read(MemReqPtr &req, uint8_t *data);
+ virtual Fault * write(MemReqPtr &req, const uint8_t *data);
bool cpuIntrPending() const;
void cpuIntrAck() { cpuIntrClear(); }
diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc
index 396e130af..1175172c4 100644
--- a/dev/pciconfigall.cc
+++ b/dev/pciconfigall.cc
@@ -95,7 +95,7 @@ PciConfigAll::startup()
}
-Fault
+Fault *
PciConfigAll::read(MemReqPtr &req, uint8_t *data)
{
@@ -112,16 +112,16 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
switch (req->size) {
// case sizeof(uint64_t):
// *(uint64_t*)data = 0xFFFFFFFFFFFFFFFF;
- // return No_Fault;
+ // return NoFault;
case sizeof(uint32_t):
*(uint32_t*)data = 0xFFFFFFFF;
- return No_Fault;
+ return NoFault;
case sizeof(uint16_t):
*(uint16_t*)data = 0xFFFF;
- return No_Fault;
+ return NoFault;
case sizeof(uint8_t):
*(uint8_t*)data = 0xFF;
- return No_Fault;
+ return NoFault;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
@@ -131,7 +131,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
case sizeof(uint16_t):
case sizeof(uint8_t):
devices[device][func]->readConfig(reg, req->size, data);
- return No_Fault;
+ return NoFault;
default:
panic("invalid access size(?) for PCI configspace!\n");
}
@@ -140,10 +140,10 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
DPRINTFN("PCI Configspace ERROR: read daddr=%#x size=%d\n",
daddr, req->size);
- return No_Fault;
+ return NoFault;
}
-Fault
+Fault *
PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
{
Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
@@ -164,7 +164,7 @@ PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
devices[device][func]->writeConfig(reg, req->size, data);
- return No_Fault;
+ return NoFault;
}
void
diff --git a/dev/pciconfigall.hh b/dev/pciconfigall.hh
index c6a0241d8..6df033286 100644
--- a/dev/pciconfigall.hh
+++ b/dev/pciconfigall.hh
@@ -103,7 +103,7 @@ class PciConfigAll : public PioDevice
* @param data Return the field read.
* @return The fault condition of the access.
*/
- virtual Fault read(MemReqPtr &req, uint8_t *data);
+ virtual Fault * read(MemReqPtr &req, uint8_t *data);
/**
* Write to PCI config spcae. If the device does not exit the simulator
@@ -114,7 +114,7 @@ class PciConfigAll : public PioDevice
* @return The fault condition of the access.
*/
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
* Start up function to check if more than one person is using an interrupt line
diff --git a/dev/pcidev.cc b/dev/pcidev.cc
index 1d9ea137d..c469e716a 100644
--- a/dev/pcidev.cc
+++ b/dev/pcidev.cc
@@ -70,59 +70,59 @@ PciDev::PciDev(Params *p)
p->configSpace->registerDevice(p->deviceNum, p->functionNum, this);
}
-Fault
+Fault *
PciDev::read(MemReqPtr &req, uint8_t *data)
-{ return No_Fault; }
+{ return NoFault; }
-Fault
+Fault *
PciDev::write(MemReqPtr &req, const uint8_t *data)
-{ return No_Fault; }
+{ return NoFault; }
-Fault
+Fault *
PciDev::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
-Fault
+Fault *
PciDev::readBar1(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
-Fault
+Fault *
PciDev::readBar2(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
-Fault
+Fault *
PciDev::readBar3(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
-Fault
+Fault *
PciDev::readBar4(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
-Fault
+Fault *
PciDev::readBar5(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
-Fault
+Fault *
PciDev::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
-Fault
+Fault *
PciDev::writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
-Fault
+Fault *
PciDev::writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
-Fault
+Fault *
PciDev::writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
-Fault
+Fault *
PciDev::writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
-Fault
+Fault *
PciDev::writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
diff --git a/dev/pcidev.hh b/dev/pcidev.hh
index efc805b3f..c8d9685c1 100644
--- a/dev/pcidev.hh
+++ b/dev/pcidev.hh
@@ -189,37 +189,37 @@ class PciDev : public DmaDevice
*/
PciDev(Params *params);
- virtual Fault read(MemReqPtr &req, uint8_t *data);
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault * read(MemReqPtr &req, uint8_t *data);
+ virtual Fault * write(MemReqPtr &req, const uint8_t *data);
public:
/**
* Implement the read/write as BAR accesses
*/
- Fault readBar(MemReqPtr &req, uint8_t *data);
- Fault writeBar(MemReqPtr &req, const uint8_t *data);
+ Fault * readBar(MemReqPtr &req, uint8_t *data);
+ Fault * writeBar(MemReqPtr &req, const uint8_t *data);
public:
/**
* Read from a specific BAR
*/
- virtual Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
- virtual Fault readBar1(MemReqPtr &req, Addr daddr, uint8_t *data);
- virtual Fault readBar2(MemReqPtr &req, Addr daddr, uint8_t *data);
- virtual Fault readBar3(MemReqPtr &req, Addr daddr, uint8_t *data);
- virtual Fault readBar4(MemReqPtr &req, Addr daddr, uint8_t *data);
- virtual Fault readBar5(MemReqPtr &req, Addr daddr, uint8_t *data);
+ virtual Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
+ virtual Fault * readBar1(MemReqPtr &req, Addr daddr, uint8_t *data);
+ virtual Fault * readBar2(MemReqPtr &req, Addr daddr, uint8_t *data);
+ virtual Fault * readBar3(MemReqPtr &req, Addr daddr, uint8_t *data);
+ virtual Fault * readBar4(MemReqPtr &req, Addr daddr, uint8_t *data);
+ virtual Fault * readBar5(MemReqPtr &req, Addr daddr, uint8_t *data);
public:
/**
* Write to a specific BAR
*/
- virtual Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
- virtual Fault writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data);
- virtual Fault writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data);
- virtual Fault writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data);
- virtual Fault writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data);
- virtual Fault writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data);
+ virtual Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
+ virtual Fault * writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data);
+ virtual Fault * writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data);
+ virtual Fault * writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data);
+ virtual Fault * writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data);
+ virtual Fault * writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data);
public:
/**
@@ -257,7 +257,7 @@ class PciDev : public DmaDevice
virtual void unserialize(Checkpoint *cp, const std::string &section);
};
-inline Fault
+inline Fault *
PciDev::readBar(MemReqPtr &req, uint8_t *data)
{
if (isBAR(req->paddr, 0))
@@ -272,10 +272,10 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data)
return readBar4(req, req->paddr - BARAddrs[4], data);
if (isBAR(req->paddr, 5))
return readBar5(req, req->paddr - BARAddrs[5], data);
- return Machine_Check_Fault;
+ return MachineCheckFault;
}
-inline Fault
+inline Fault *
PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
{
if (isBAR(req->paddr, 0))
@@ -290,7 +290,7 @@ PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
return writeBar4(req, req->paddr - BARAddrs[4], data);
if (isBAR(req->paddr, 5))
return writeBar5(req, req->paddr - BARAddrs[5], data);
- return Machine_Check_Fault;
+ return MachineCheckFault;
}
#endif // __DEV_PCIDEV_HH__
diff --git a/dev/sinic.cc b/dev/sinic.cc
index 69239df32..e79f80678 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -361,23 +361,23 @@ Device::prepareWrite(int cpu, int index)
/**
* I/O read of device register
*/
-Fault
+Fault *
Device::read(MemReqPtr &req, uint8_t *data)
{
assert(config.command & PCI_CMD_MSE);
- Fault fault = readBar(req, data);
+ Fault * fault = readBar(req, data);
- if (fault == Machine_Check_Fault) {
+ if (fault == MachineCheckFault) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
- return Machine_Check_Fault;
+ return MachineCheckFault;
}
return fault;
}
-Fault
+Fault *
Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
{
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
@@ -421,13 +421,13 @@ Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
if (raddr == Regs::IntrStatus)
devIntrClear();
- return No_Fault;
+ return NoFault;
}
/**
* IPR read of device register
*/
-Fault
+Fault *
Device::iprRead(Addr daddr, int cpu, uint64_t &result)
{
if (!regValid(daddr))
@@ -451,29 +451,29 @@ Device::iprRead(Addr daddr, int cpu, uint64_t &result)
DPRINTF(EthernetPIO, "IPR read %s: cpu=%s da=%#x val=%#x\n",
info.name, cpu, result);
- return No_Fault;
+ return NoFault;
}
/**
* I/O write of device register
*/
-Fault
+Fault *
Device::write(MemReqPtr &req, const uint8_t *data)
{
assert(config.command & PCI_CMD_MSE);
- Fault fault = writeBar(req, data);
+ Fault * fault = writeBar(req, data);
- if (fault == Machine_Check_Fault) {
+ if (fault == MachineCheckFault) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
- return Machine_Check_Fault;
+ return MachineCheckFault;
}
return fault;
}
-Fault
+Fault *
Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
{
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
@@ -508,7 +508,7 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
if (!pioDelayWrite || !info.delay_write)
regWrite(daddr, cpu, data);
- return No_Fault;
+ return NoFault;
}
void
diff --git a/dev/sinic.hh b/dev/sinic.hh
index af2f109a4..7935a7cdc 100644
--- a/dev/sinic.hh
+++ b/dev/sinic.hh
@@ -271,15 +271,15 @@ class Device : public Base
* Memory Interface
*/
public:
- virtual Fault read(MemReqPtr &req, uint8_t *data);
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault * read(MemReqPtr &req, uint8_t *data);
+ virtual Fault * write(MemReqPtr &req, const uint8_t *data);
void prepareIO(int cpu, int index);
void prepareRead(int cpu, int index);
void prepareWrite(int cpu, int index);
- Fault iprRead(Addr daddr, int cpu, uint64_t &result);
- Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
- Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
+ Fault * iprRead(Addr daddr, int cpu, uint64_t &result);
+ Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
+ Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
void regWrite(Addr daddr, int cpu, const uint8_t *data);
Tick cacheAccess(MemReqPtr &req);
diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
index 2287a2a3d..4cda9ec36 100644
--- a/dev/tsunami_cchip.cc
+++ b/dev/tsunami_cchip.cc
@@ -76,7 +76,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
tsunami->cchip = this;
}
-Fault
+Fault *
TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size);
@@ -92,81 +92,81 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
if (daddr & TSDEV_CC_BDIMS)
{
*(uint64_t*)data = dim[(daddr >> 4) & 0x3F];
- return No_Fault;
+ return NoFault;
}
if (daddr & TSDEV_CC_BDIRS)
{
*(uint64_t*)data = dir[(daddr >> 4) & 0x3F];
- return No_Fault;
+ return NoFault;
}
switch(regnum) {
case TSDEV_CC_CSR:
*(uint64_t*)data = 0x0;
- return No_Fault;
+ return NoFault;
case TSDEV_CC_MTR:
panic("TSDEV_CC_MTR not implemeted\n");
- return No_Fault;
+ return NoFault;
case TSDEV_CC_MISC:
*(uint64_t*)data = (ipint << 8) & 0xF |
(itint << 4) & 0xF |
(xc->cpu_id & 0x3);
- return No_Fault;
+ return NoFault;
case TSDEV_CC_AAR0:
case TSDEV_CC_AAR1:
case TSDEV_CC_AAR2:
case TSDEV_CC_AAR3:
*(uint64_t*)data = 0;
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIM0:
*(uint64_t*)data = dim[0];
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIM1:
*(uint64_t*)data = dim[1];
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIM2:
*(uint64_t*)data = dim[2];
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIM3:
*(uint64_t*)data = dim[3];
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIR0:
*(uint64_t*)data = dir[0];
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIR1:
*(uint64_t*)data = dir[1];
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIR2:
*(uint64_t*)data = dir[2];
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIR3:
*(uint64_t*)data = dir[3];
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DRIR:
*(uint64_t*)data = drir;
- return No_Fault;
+ return NoFault;
case TSDEV_CC_PRBEN:
panic("TSDEV_CC_PRBEN not implemented\n");
- return No_Fault;
+ return NoFault;
case TSDEV_CC_IIC0:
case TSDEV_CC_IIC1:
case TSDEV_CC_IIC2:
case TSDEV_CC_IIC3:
panic("TSDEV_CC_IICx not implemented\n");
- return No_Fault;
+ return NoFault;
case TSDEV_CC_MPR0:
case TSDEV_CC_MPR1:
case TSDEV_CC_MPR2:
case TSDEV_CC_MPR3:
panic("TSDEV_CC_MPRx not implemented\n");
- return No_Fault;
+ return NoFault;
case TSDEV_CC_IPIR:
*(uint64_t*)data = ipint;
- return No_Fault;
+ return NoFault;
case TSDEV_CC_ITIR:
*(uint64_t*)data = itint;
- return No_Fault;
+ return NoFault;
default:
panic("default in cchip read reached, accessing 0x%x\n");
} // uint64_t
@@ -179,7 +179,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
*(uint32_t*)data = drir;
} else
panic("invalid access size(?) for tsunami register!\n");
- return No_Fault;
+ return NoFault;
case sizeof(uint16_t):
case sizeof(uint8_t):
default:
@@ -187,10 +187,10 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
}
DPRINTFN("Tsunami CChip ERROR: read regnum=%#x size=%d\n", regnum, req->size);
- return No_Fault;
+ return NoFault;
}
-Fault
+Fault *
TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
{
DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n",
@@ -243,16 +243,16 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
}
}
- return No_Fault;
+ return NoFault;
}
switch(regnum) {
case TSDEV_CC_CSR:
panic("TSDEV_CC_CSR write\n");
- return No_Fault;
+ return NoFault;
case TSDEV_CC_MTR:
panic("TSDEV_CC_MTR write not implemented\n");
- return No_Fault;
+ return NoFault;
case TSDEV_CC_MISC:
uint64_t ipreq;
ipreq = (*(uint64_t*)data >> 12) & 0xF;
@@ -285,13 +285,13 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
if(!supportedWrite)
panic("TSDEV_CC_MISC write not implemented\n");
- return No_Fault;
+ return NoFault;
case TSDEV_CC_AAR0:
case TSDEV_CC_AAR1:
case TSDEV_CC_AAR2:
case TSDEV_CC_AAR3:
panic("TSDEV_CC_AARx write not implemeted\n");
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIM0:
case TSDEV_CC_DIM1:
case TSDEV_CC_DIM2:
@@ -341,7 +341,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
}
}
- return No_Fault;
+ return NoFault;
case TSDEV_CC_DIR0:
case TSDEV_CC_DIR1:
case TSDEV_CC_DIR2:
@@ -363,13 +363,13 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
panic("TSDEV_CC_MPRx write not implemented\n");
case TSDEV_CC_IPIR:
clearIPI(*(uint64_t*)data);
- return No_Fault;
+ return NoFault;
case TSDEV_CC_ITIR:
clearITI(*(uint64_t*)data);
- return No_Fault;
+ return NoFault;
case TSDEV_CC_IPIQ:
reqIPI(*(uint64_t*)data);
- return No_Fault;
+ return NoFault;
default:
panic("default in cchip read reached, accessing 0x%x\n");
}
@@ -384,7 +384,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
- return No_Fault;
+ return NoFault;
}
void
diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh
index d88ad375f..dadbdb0e3 100644
--- a/dev/tsunami_cchip.hh
+++ b/dev/tsunami_cchip.hh
@@ -105,7 +105,7 @@ class TsunamiCChip : public PioDevice
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
- virtual Fault read(MemReqPtr &req, uint8_t *data);
+ virtual Fault * read(MemReqPtr &req, uint8_t *data);
/**
@@ -114,7 +114,7 @@ class TsunamiCChip : public PioDevice
* @param data The data to write.
* @return The fault condition of the access.
*/
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
* post an RTC interrupt to the CPU
diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc
index 724a5bfb9..0d0d27570 100644
--- a/dev/tsunami_io.cc
+++ b/dev/tsunami_io.cc
@@ -444,7 +444,7 @@ TsunamiIO::frequency() const
return Clock::Frequency / clockInterval;
}
-Fault
+Fault *
TsunamiIO::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n",
@@ -459,38 +459,38 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
// PIC1 mask read
case TSDEV_PIC1_MASK:
*(uint8_t*)data = ~mask1;
- return No_Fault;
+ return NoFault;
case TSDEV_PIC2_MASK:
*(uint8_t*)data = ~mask2;
- return No_Fault;
+ return NoFault;
case TSDEV_PIC1_ISR:
// !!! If this is modified 64bit case needs to be too
// Pal code has to do a 64 bit physical read because there is
// no load physical byte instruction
*(uint8_t*)data = picr;
- return No_Fault;
+ return NoFault;
case TSDEV_PIC2_ISR:
// PIC2 not implemnted... just return 0
*(uint8_t*)data = 0x00;
- return No_Fault;
+ return NoFault;
case TSDEV_TMR0_DATA:
pitimer.counter0.read(data);
- return No_Fault;
+ return NoFault;
case TSDEV_TMR1_DATA:
pitimer.counter1.read(data);
- return No_Fault;
+ return NoFault;
case TSDEV_TMR2_DATA:
pitimer.counter2.read(data);
- return No_Fault;
+ return NoFault;
case TSDEV_RTC_DATA:
rtc.readData(data);
- return No_Fault;
+ return NoFault;
case TSDEV_CTRL_PORTB:
if (pitimer.counter2.outputHigh())
*data = PORTB_SPKR_HIGH;
else
*data = 0x00;
- return No_Fault;
+ return NoFault;
default:
panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
}
@@ -506,7 +506,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
// Pal code has to do a 64 bit physical read because there is
// no load physical byte instruction
*(uint64_t*)data = (uint64_t)picr;
- return No_Fault;
+ return NoFault;
default:
panic("I/O Read - invalid size - va %#x size %d\n",
req->vaddr, req->size);
@@ -518,10 +518,10 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
}
panic("I/O Read - va%#x size %d\n", req->vaddr, req->size);
- return No_Fault;
+ return NoFault;
}
-Fault
+Fault *
TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
{
@@ -550,63 +550,63 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
tsunami->cchip->clearDRIR(55);
DPRINTF(Tsunami, "clearing pic interrupt\n");
}
- return No_Fault;
+ return NoFault;
case TSDEV_PIC2_MASK:
mask2 = *(uint8_t*)data;
//PIC2 Not implemented to interrupt
- return No_Fault;
+ return NoFault;
case TSDEV_PIC1_ACK:
// clear the interrupt on the PIC
picr &= ~(1 << (*(uint8_t*)data & 0xF));
if (!(picr & mask1))
tsunami->cchip->clearDRIR(55);
- return No_Fault;
+ return NoFault;
case TSDEV_DMA1_CMND:
- return No_Fault;
+ return NoFault;
case TSDEV_DMA2_CMND:
- return No_Fault;
+ return NoFault;
case TSDEV_DMA1_MMASK:
- return No_Fault;
+ return NoFault;
case TSDEV_DMA2_MMASK:
- return No_Fault;
+ return NoFault;
case TSDEV_PIC2_ACK:
- return No_Fault;
+ return NoFault;
case TSDEV_DMA1_RESET:
- return No_Fault;
+ return NoFault;
case TSDEV_DMA2_RESET:
- return No_Fault;
+ return NoFault;
case TSDEV_DMA1_MODE:
mode1 = *(uint8_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_DMA2_MODE:
mode2 = *(uint8_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_DMA1_MASK:
case TSDEV_DMA2_MASK:
- return No_Fault;
+ return NoFault;
case TSDEV_TMR0_DATA:
pitimer.counter0.write(data);
- return No_Fault;
+ return NoFault;
case TSDEV_TMR1_DATA:
pitimer.counter1.write(data);
- return No_Fault;
+ return NoFault;
case TSDEV_TMR2_DATA:
pitimer.counter2.write(data);
- return No_Fault;
+ return NoFault;
case TSDEV_TMR_CTRL:
pitimer.writeControl(data);
- return No_Fault;
+ return NoFault;
case TSDEV_RTC_ADDR:
rtc.writeAddr(data);
- return No_Fault;
+ return NoFault;
case TSDEV_KBD:
- return No_Fault;
+ return NoFault;
case TSDEV_RTC_DATA:
rtc.writeData(data);
- return No_Fault;
+ return NoFault;
case TSDEV_CTRL_PORTB:
// System Control Port B not implemented
- return No_Fault;
+ return NoFault;
default:
panic("I/O Write - va%#x size %d data %#x\n", req->vaddr, req->size, (int)*data);
}
@@ -619,7 +619,7 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
}
- return No_Fault;
+ return NoFault;
}
void
diff --git a/dev/tsunami_io.hh b/dev/tsunami_io.hh
index b024ecd14..3b26ebfaa 100644
--- a/dev/tsunami_io.hh
+++ b/dev/tsunami_io.hh
@@ -330,7 +330,7 @@ class TsunamiIO : public PioDevice
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
- virtual Fault read(MemReqPtr &req, uint8_t *data);
+ virtual Fault * read(MemReqPtr &req, uint8_t *data);
/**
* Process a write to one of the devices we emulate.
@@ -338,7 +338,7 @@ class TsunamiIO : public PioDevice
* @param data The data to write.
* @return The fault condition of the access.
*/
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
* Post an PIC interrupt to the CPU via the CChip
diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc
index e61137170..a4c04a79f 100644
--- a/dev/tsunami_pchip.cc
+++ b/dev/tsunami_pchip.cc
@@ -76,7 +76,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
tsunami->pchip = this;
}
-Fault
+Fault *
TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n",
@@ -90,60 +90,60 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
switch(daddr) {
case TSDEV_PC_WSBA0:
*(uint64_t*)data = wsba[0];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA1:
*(uint64_t*)data = wsba[1];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA2:
*(uint64_t*)data = wsba[2];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA3:
*(uint64_t*)data = wsba[3];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM0:
*(uint64_t*)data = wsm[0];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM1:
*(uint64_t*)data = wsm[1];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM2:
*(uint64_t*)data = wsm[2];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM3:
*(uint64_t*)data = wsm[3];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA0:
*(uint64_t*)data = tba[0];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA1:
*(uint64_t*)data = tba[1];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA2:
*(uint64_t*)data = tba[2];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA3:
*(uint64_t*)data = tba[3];
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PCTL:
*(uint64_t*)data = pctl;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PLAT:
panic("PC_PLAT not implemented\n");
case TSDEV_PC_RES:
panic("PC_RES not implemented\n");
case TSDEV_PC_PERROR:
*(uint64_t*)data = 0x00;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PERRMASK:
*(uint64_t*)data = 0x00;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PERRSET:
panic("PC_PERRSET not implemented\n");
case TSDEV_PC_TLBIV:
panic("PC_TLBIV not implemented\n");
case TSDEV_PC_TLBIA:
*(uint64_t*)data = 0x00; // shouldn't be readable, but linux
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PMONCTL:
panic("PC_PMONCTL not implemented\n");
case TSDEV_PC_PMONCNT:
@@ -162,10 +162,10 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
}
DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size);
- return No_Fault;
+ return NoFault;
}
-Fault
+Fault *
TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
{
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
@@ -179,49 +179,49 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
switch(daddr) {
case TSDEV_PC_WSBA0:
wsba[0] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA1:
wsba[1] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA2:
wsba[2] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSBA3:
wsba[3] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM0:
wsm[0] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM1:
wsm[1] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM2:
wsm[2] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_WSM3:
wsm[3] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA0:
tba[0] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA1:
tba[1] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA2:
tba[2] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_TBA3:
tba[3] = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PCTL:
pctl = *(uint64_t*)data;
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PLAT:
panic("PC_PLAT not implemented\n");
case TSDEV_PC_RES:
panic("PC_RES not implemented\n");
case TSDEV_PC_PERROR:
- return No_Fault;
+ return NoFault;
case TSDEV_PC_PERRMASK:
panic("PC_PERRMASK not implemented\n");
case TSDEV_PC_PERRSET:
@@ -229,7 +229,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
case TSDEV_PC_TLBIV:
panic("PC_TLBIV not implemented\n");
case TSDEV_PC_TLBIA:
- return No_Fault; // value ignored, supposted to invalidate SG TLB
+ return NoFault; // value ignored, supposted to invalidate SG TLB
case TSDEV_PC_PMONCTL:
panic("PC_PMONCTL not implemented\n");
case TSDEV_PC_PMONCNT:
@@ -249,7 +249,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
- return No_Fault;
+ return NoFault;
}
#define DMA_ADDR_MASK ULL(0x3ffffffff)
diff --git a/dev/tsunami_pchip.hh b/dev/tsunami_pchip.hh
index c1d95431b..ff888bea1 100644
--- a/dev/tsunami_pchip.hh
+++ b/dev/tsunami_pchip.hh
@@ -99,7 +99,7 @@ class TsunamiPChip : public PioDevice
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
- virtual Fault read(MemReqPtr &req, uint8_t *data);
+ virtual Fault * read(MemReqPtr &req, uint8_t *data);
/**
* Process a write to the PChip.
@@ -107,7 +107,7 @@ class TsunamiPChip : public PioDevice
* @param data The data to write.
* @return The fault condition of the access.
*/
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
* Serialize this object to the given output stream.
diff --git a/dev/uart.hh b/dev/uart.hh
index 145b9ca9e..96c22025c 100644
--- a/dev/uart.hh
+++ b/dev/uart.hh
@@ -57,8 +57,8 @@ class Uart : public PioDevice
Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
Platform *p);
- virtual Fault read(MemReqPtr &req, uint8_t *data) = 0;
- virtual Fault write(MemReqPtr &req, const uint8_t *data) = 0;
+ virtual Fault * read(MemReqPtr &req, uint8_t *data) = 0;
+ virtual Fault * write(MemReqPtr &req, const uint8_t *data) = 0;
/**
diff --git a/dev/uart8250.cc b/dev/uart8250.cc
index 71f429069..a2e782189 100644
--- a/dev/uart8250.cc
+++ b/dev/uart8250.cc
@@ -111,7 +111,7 @@ Uart8250::Uart8250(const string &name, SimConsole *c, MemoryController *mmu,
}
-Fault
+Fault *
Uart8250::read(MemReqPtr &req, uint8_t *data)
{
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
@@ -183,11 +183,11 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
break;
}
- return No_Fault;
+ return NoFault;
}
-Fault
+Fault *
Uart8250::write(MemReqPtr &req, const uint8_t *data)
{
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
@@ -255,7 +255,7 @@ Uart8250::write(MemReqPtr &req, const uint8_t *data)
panic("Tried to access a UART port that doesn't exist\n");
break;
}
- return No_Fault;
+ return NoFault;
}
void
diff --git a/dev/uart8250.hh b/dev/uart8250.hh
index 88abf8e24..a0e2d344a 100644
--- a/dev/uart8250.hh
+++ b/dev/uart8250.hh
@@ -82,8 +82,8 @@ class Uart8250 : public Uart
Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency,
Platform *p);
- virtual Fault read(MemReqPtr &req, uint8_t *data);
- virtual Fault write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault * read(MemReqPtr &req, uint8_t *data);
+ virtual Fault * write(MemReqPtr &req, const uint8_t *data);
/**
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-26 11:01:59 +0000