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-rw-r--r--dev/alpha_console.cc4
-rw-r--r--dev/alpha_console.hh4
-rw-r--r--dev/baddev.cc4
-rw-r--r--dev/baddev.hh4
-rw-r--r--dev/ide_ctrl.cc4
-rw-r--r--dev/ide_ctrl.hh4
-rw-r--r--dev/isa_fake.cc4
-rw-r--r--dev/isa_fake.hh4
-rw-r--r--dev/ns_gige.cc4
-rw-r--r--dev/ns_gige.hh4
-rw-r--r--dev/pciconfigall.cc4
-rw-r--r--dev/pciconfigall.hh4
-rw-r--r--dev/pcidev.cc28
-rw-r--r--dev/pcidev.hh36
-rw-r--r--dev/sinic.cc14
-rw-r--r--dev/sinic.hh10
-rw-r--r--dev/tsunami_cchip.cc4
-rw-r--r--dev/tsunami_cchip.hh4
-rw-r--r--dev/tsunami_io.cc4
-rw-r--r--dev/tsunami_io.hh4
-rw-r--r--dev/tsunami_pchip.cc4
-rw-r--r--dev/tsunami_pchip.hh4
-rw-r--r--dev/uart.hh4
-rw-r--r--dev/uart8250.cc4
-rw-r--r--dev/uart8250.hh4
25 files changed, 86 insertions, 86 deletions
diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc
index a7ef8f641..0f36e63fb 100644
--- a/dev/alpha_console.cc
+++ b/dev/alpha_console.cc
@@ -100,7 +100,7 @@ AlphaConsole::startup()
alphaAccess->intrClockFrequency = platform->intrFrequency();
}
-Fault *
+Fault
AlphaConsole::read(MemReqPtr &req, uint8_t *data)
{
memset(data, 0, req->size);
@@ -190,7 +190,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
-Fault *
+Fault
AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
{
uint64_t val;
diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh
index 75f0a3a67..74ad795f0 100644
--- a/dev/alpha_console.hh
+++ b/dev/alpha_console.hh
@@ -110,8 +110,8 @@ class AlphaConsole : public PioDevice
/**
* memory mapped reads and writes
*/
- virtual Fault * read(MemReqPtr &req, uint8_t *data);
- virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault read(MemReqPtr &req, uint8_t *data);
+ virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* standard serialization routines for checkpointing
diff --git a/dev/baddev.cc b/dev/baddev.cc
index 62871e348..87d683a5d 100644
--- a/dev/baddev.cc
+++ b/dev/baddev.cc
@@ -62,7 +62,7 @@ BadDevice::BadDevice(const string &name, Addr a, MemoryController *mmu,
}
-Fault *
+Fault
BadDevice::read(MemReqPtr &req, uint8_t *data)
{
@@ -70,7 +70,7 @@ BadDevice::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
-Fault *
+Fault
BadDevice::write(MemReqPtr &req, const uint8_t *data)
{
panic("Device %s not imlpmented\n", devname);
diff --git a/dev/baddev.hh b/dev/baddev.hh
index b7b67e31a..c2a204c05 100644
--- a/dev/baddev.hh
+++ b/dev/baddev.hh
@@ -71,7 +71,7 @@ class BadDevice : public PioDevice
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
- virtual Fault * read(MemReqPtr &req, uint8_t *data);
+ virtual Fault read(MemReqPtr &req, uint8_t *data);
/**
* On a write event we just panic aand hopefully print a
@@ -80,7 +80,7 @@ class BadDevice : public PioDevice
* @param data The data to write.
* @return The fault condition of the access.
*/
- virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* Return how long this access will take.
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index 18c988b81..56682a224 100644
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -391,7 +391,7 @@ IdeController::writeConfig(int offset, int size, const uint8_t *data)
}
}
-Fault *
+Fault
IdeController::read(MemReqPtr &req, uint8_t *data)
{
Addr offset;
@@ -461,7 +461,7 @@ IdeController::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
-Fault *
+Fault
IdeController::write(MemReqPtr &req, const uint8_t *data)
{
Addr offset;
diff --git a/dev/ide_ctrl.hh b/dev/ide_ctrl.hh
index 72523f57c..0fbaf9207 100644
--- a/dev/ide_ctrl.hh
+++ b/dev/ide_ctrl.hh
@@ -213,7 +213,7 @@ class IdeController : public PciDev
* @param data Return the field read.
* @return The fault condition of the access.
*/
- virtual Fault * read(MemReqPtr &req, uint8_t *data);
+ virtual Fault read(MemReqPtr &req, uint8_t *data);
/**
* Write to the mmapped I/O control registers.
@@ -221,7 +221,7 @@ class IdeController : public PciDev
* @param data The data to write.
* @return The fault condition of the access.
*/
- virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* Serialize this object to the given output stream.
diff --git a/dev/isa_fake.cc b/dev/isa_fake.cc
index 117c9e5ad..2afebbded 100644
--- a/dev/isa_fake.cc
+++ b/dev/isa_fake.cc
@@ -60,7 +60,7 @@ IsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu,
}
}
-Fault *
+Fault
IsaFake::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n",
@@ -93,7 +93,7 @@ IsaFake::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
-Fault *
+Fault
IsaFake::write(MemReqPtr &req, const uint8_t *data)
{
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
diff --git a/dev/isa_fake.hh b/dev/isa_fake.hh
index 60ca5f90a..290b24b54 100644
--- a/dev/isa_fake.hh
+++ b/dev/isa_fake.hh
@@ -65,14 +65,14 @@ class IsaFake : public PioDevice
* @param req The memory request.
* @param data Where to put the data.
*/
- virtual Fault * read(MemReqPtr &req, uint8_t *data);
+ virtual Fault read(MemReqPtr &req, uint8_t *data);
/**
* All writes are simply ignored.
* @param req The memory request.
* @param data the data to not write.
*/
- virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* Return how long this access will take.
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index 02eb72ca4..4b08d8497 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -557,7 +557,7 @@ NSGigE::writeConfig(int offset, int size, const uint8_t* data)
* This reads the device registers, which are detailed in the NS83820
* spec sheet
*/
-Fault *
+Fault
NSGigE::read(MemReqPtr &req, uint8_t *data)
{
assert(ioEnable);
@@ -786,7 +786,7 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
-Fault *
+Fault
NSGigE::write(MemReqPtr &req, const uint8_t *data)
{
assert(ioEnable);
diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index a14fde146..cdd8e4b9e 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -395,8 +395,8 @@ class NSGigE : public PciDev
virtual void writeConfig(int offset, int size, const uint8_t *data);
virtual void readConfig(int offset, int size, uint8_t *data);
- virtual Fault * read(MemReqPtr &req, uint8_t *data);
- virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault read(MemReqPtr &req, uint8_t *data);
+ virtual Fault write(MemReqPtr &req, const uint8_t *data);
bool cpuIntrPending() const;
void cpuIntrAck() { cpuIntrClear(); }
diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc
index c581e1561..d55084fa5 100644
--- a/dev/pciconfigall.cc
+++ b/dev/pciconfigall.cc
@@ -96,7 +96,7 @@ PciConfigAll::startup()
}
-Fault *
+Fault
PciConfigAll::read(MemReqPtr &req, uint8_t *data)
{
@@ -144,7 +144,7 @@ PciConfigAll::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
-Fault *
+Fault
PciConfigAll::write(MemReqPtr &req, const uint8_t *data)
{
Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask));
diff --git a/dev/pciconfigall.hh b/dev/pciconfigall.hh
index 6df033286..c6a0241d8 100644
--- a/dev/pciconfigall.hh
+++ b/dev/pciconfigall.hh
@@ -103,7 +103,7 @@ class PciConfigAll : public PioDevice
* @param data Return the field read.
* @return The fault condition of the access.
*/
- virtual Fault * read(MemReqPtr &req, uint8_t *data);
+ virtual Fault read(MemReqPtr &req, uint8_t *data);
/**
* Write to PCI config spcae. If the device does not exit the simulator
@@ -114,7 +114,7 @@ class PciConfigAll : public PioDevice
* @return The fault condition of the access.
*/
- virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* Start up function to check if more than one person is using an interrupt line
diff --git a/dev/pcidev.cc b/dev/pcidev.cc
index c469e716a..a05ee3803 100644
--- a/dev/pcidev.cc
+++ b/dev/pcidev.cc
@@ -70,59 +70,59 @@ PciDev::PciDev(Params *p)
p->configSpace->registerDevice(p->deviceNum, p->functionNum, this);
}
-Fault *
+Fault
PciDev::read(MemReqPtr &req, uint8_t *data)
{ return NoFault; }
-Fault *
+Fault
PciDev::write(MemReqPtr &req, const uint8_t *data)
{ return NoFault; }
-Fault *
+Fault
PciDev::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
-Fault *
+Fault
PciDev::readBar1(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
-Fault *
+Fault
PciDev::readBar2(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
-Fault *
+Fault
PciDev::readBar3(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
-Fault *
+Fault
PciDev::readBar4(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
-Fault *
+Fault
PciDev::readBar5(MemReqPtr &req, Addr daddr, uint8_t *data)
{ panic("not implemented"); }
-Fault *
+Fault
PciDev::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
-Fault *
+Fault
PciDev::writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
-Fault *
+Fault
PciDev::writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
-Fault *
+Fault
PciDev::writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
-Fault *
+Fault
PciDev::writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
-Fault *
+Fault
PciDev::writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data)
{ panic("not implemented"); }
diff --git a/dev/pcidev.hh b/dev/pcidev.hh
index c8d9685c1..9427463bf 100644
--- a/dev/pcidev.hh
+++ b/dev/pcidev.hh
@@ -189,37 +189,37 @@ class PciDev : public DmaDevice
*/
PciDev(Params *params);
- virtual Fault * read(MemReqPtr &req, uint8_t *data);
- virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault read(MemReqPtr &req, uint8_t *data);
+ virtual Fault write(MemReqPtr &req, const uint8_t *data);
public:
/**
* Implement the read/write as BAR accesses
*/
- Fault * readBar(MemReqPtr &req, uint8_t *data);
- Fault * writeBar(MemReqPtr &req, const uint8_t *data);
+ Fault readBar(MemReqPtr &req, uint8_t *data);
+ Fault writeBar(MemReqPtr &req, const uint8_t *data);
public:
/**
* Read from a specific BAR
*/
- virtual Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
- virtual Fault * readBar1(MemReqPtr &req, Addr daddr, uint8_t *data);
- virtual Fault * readBar2(MemReqPtr &req, Addr daddr, uint8_t *data);
- virtual Fault * readBar3(MemReqPtr &req, Addr daddr, uint8_t *data);
- virtual Fault * readBar4(MemReqPtr &req, Addr daddr, uint8_t *data);
- virtual Fault * readBar5(MemReqPtr &req, Addr daddr, uint8_t *data);
+ virtual Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
+ virtual Fault readBar1(MemReqPtr &req, Addr daddr, uint8_t *data);
+ virtual Fault readBar2(MemReqPtr &req, Addr daddr, uint8_t *data);
+ virtual Fault readBar3(MemReqPtr &req, Addr daddr, uint8_t *data);
+ virtual Fault readBar4(MemReqPtr &req, Addr daddr, uint8_t *data);
+ virtual Fault readBar5(MemReqPtr &req, Addr daddr, uint8_t *data);
public:
/**
* Write to a specific BAR
*/
- virtual Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
- virtual Fault * writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data);
- virtual Fault * writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data);
- virtual Fault * writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data);
- virtual Fault * writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data);
- virtual Fault * writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data);
+ virtual Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
+ virtual Fault writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data);
+ virtual Fault writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data);
+ virtual Fault writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data);
+ virtual Fault writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data);
+ virtual Fault writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data);
public:
/**
@@ -257,7 +257,7 @@ class PciDev : public DmaDevice
virtual void unserialize(Checkpoint *cp, const std::string &section);
};
-inline Fault *
+inline Fault
PciDev::readBar(MemReqPtr &req, uint8_t *data)
{
if (isBAR(req->paddr, 0))
@@ -275,7 +275,7 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data)
return MachineCheckFault;
}
-inline Fault *
+inline Fault
PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
{
if (isBAR(req->paddr, 0))
diff --git a/dev/sinic.cc b/dev/sinic.cc
index d175a1796..c499d2f49 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -357,11 +357,11 @@ Device::prepareWrite(int cpu, int index)
/**
* I/O read of device register
*/
-Fault *
+Fault
Device::read(MemReqPtr &req, uint8_t *data)
{
assert(config.command & PCI_CMD_MSE);
- Fault * fault = readBar(req, data);
+ Fault fault = readBar(req, data);
if (fault == MachineCheckFault) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
@@ -373,7 +373,7 @@ Device::read(MemReqPtr &req, uint8_t *data)
return fault;
}
-Fault *
+Fault
Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
{
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
@@ -423,7 +423,7 @@ Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data)
/**
* IPR read of device register
*/
-Fault *
+Fault
Device::iprRead(Addr daddr, int cpu, uint64_t &result)
{
if (!regValid(daddr))
@@ -453,11 +453,11 @@ Device::iprRead(Addr daddr, int cpu, uint64_t &result)
/**
* I/O write of device register
*/
-Fault *
+Fault
Device::write(MemReqPtr &req, const uint8_t *data)
{
assert(config.command & PCI_CMD_MSE);
- Fault * fault = writeBar(req, data);
+ Fault fault = writeBar(req, data);
if (fault == MachineCheckFault) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
@@ -469,7 +469,7 @@ Device::write(MemReqPtr &req, const uint8_t *data)
return fault;
}
-Fault *
+Fault
Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data)
{
int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff;
diff --git a/dev/sinic.hh b/dev/sinic.hh
index 06751a955..97ebf4c30 100644
--- a/dev/sinic.hh
+++ b/dev/sinic.hh
@@ -271,15 +271,15 @@ class Device : public Base
* Memory Interface
*/
public:
- virtual Fault * read(MemReqPtr &req, uint8_t *data);
- virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault read(MemReqPtr &req, uint8_t *data);
+ virtual Fault write(MemReqPtr &req, const uint8_t *data);
void prepareIO(int cpu, int index);
void prepareRead(int cpu, int index);
void prepareWrite(int cpu, int index);
- Fault * iprRead(Addr daddr, int cpu, uint64_t &result);
- Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
- Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
+ Fault iprRead(Addr daddr, int cpu, uint64_t &result);
+ Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
+ Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
void regWrite(Addr daddr, int cpu, const uint8_t *data);
Tick cacheAccess(MemReqPtr &req);
diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
index 10c08a7a2..4dc4413a1 100644
--- a/dev/tsunami_cchip.cc
+++ b/dev/tsunami_cchip.cc
@@ -78,7 +78,7 @@ TsunamiCChip::TsunamiCChip(const string &name, Tsunami *t, Addr a,
tsunami->cchip = this;
}
-Fault *
+Fault
TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size);
@@ -192,7 +192,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
-Fault *
+Fault
TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
{
DPRINTF(Tsunami, "write - va=%#x value=%#x size=%d \n",
diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh
index dadbdb0e3..d88ad375f 100644
--- a/dev/tsunami_cchip.hh
+++ b/dev/tsunami_cchip.hh
@@ -105,7 +105,7 @@ class TsunamiCChip : public PioDevice
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
- virtual Fault * read(MemReqPtr &req, uint8_t *data);
+ virtual Fault read(MemReqPtr &req, uint8_t *data);
/**
@@ -114,7 +114,7 @@ class TsunamiCChip : public PioDevice
* @param data The data to write.
* @return The fault condition of the access.
*/
- virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* post an RTC interrupt to the CPU
diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc
index e90bb5abc..e66d6653b 100644
--- a/dev/tsunami_io.cc
+++ b/dev/tsunami_io.cc
@@ -446,7 +446,7 @@ TsunamiIO::frequency() const
return Clock::Frequency / clockInterval;
}
-Fault *
+Fault
TsunamiIO::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n",
@@ -523,7 +523,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
-Fault *
+Fault
TsunamiIO::write(MemReqPtr &req, const uint8_t *data)
{
diff --git a/dev/tsunami_io.hh b/dev/tsunami_io.hh
index 3b26ebfaa..b024ecd14 100644
--- a/dev/tsunami_io.hh
+++ b/dev/tsunami_io.hh
@@ -330,7 +330,7 @@ class TsunamiIO : public PioDevice
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
- virtual Fault * read(MemReqPtr &req, uint8_t *data);
+ virtual Fault read(MemReqPtr &req, uint8_t *data);
/**
* Process a write to one of the devices we emulate.
@@ -338,7 +338,7 @@ class TsunamiIO : public PioDevice
* @param data The data to write.
* @return The fault condition of the access.
*/
- virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* Post an PIC interrupt to the CPU via the CChip
diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc
index 706daf9dc..46efc3dfe 100644
--- a/dev/tsunami_pchip.cc
+++ b/dev/tsunami_pchip.cc
@@ -78,7 +78,7 @@ TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
tsunami->pchip = this;
}
-Fault *
+Fault
TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
{
DPRINTF(Tsunami, "read va=%#x size=%d\n",
@@ -167,7 +167,7 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
return NoFault;
}
-Fault *
+Fault
TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
{
DPRINTF(Tsunami, "write - va=%#x size=%d \n",
diff --git a/dev/tsunami_pchip.hh b/dev/tsunami_pchip.hh
index ff888bea1..c1d95431b 100644
--- a/dev/tsunami_pchip.hh
+++ b/dev/tsunami_pchip.hh
@@ -99,7 +99,7 @@ class TsunamiPChip : public PioDevice
* @param data A pointer to write the read data to.
* @return The fault condition of the access.
*/
- virtual Fault * read(MemReqPtr &req, uint8_t *data);
+ virtual Fault read(MemReqPtr &req, uint8_t *data);
/**
* Process a write to the PChip.
@@ -107,7 +107,7 @@ class TsunamiPChip : public PioDevice
* @param data The data to write.
* @return The fault condition of the access.
*/
- virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
* Serialize this object to the given output stream.
diff --git a/dev/uart.hh b/dev/uart.hh
index 96c22025c..145b9ca9e 100644
--- a/dev/uart.hh
+++ b/dev/uart.hh
@@ -57,8 +57,8 @@ class Uart : public PioDevice
Addr a, Addr s, HierParams *hier, Bus *bus, Tick pio_latency,
Platform *p);
- virtual Fault * read(MemReqPtr &req, uint8_t *data) = 0;
- virtual Fault * write(MemReqPtr &req, const uint8_t *data) = 0;
+ virtual Fault read(MemReqPtr &req, uint8_t *data) = 0;
+ virtual Fault write(MemReqPtr &req, const uint8_t *data) = 0;
/**
diff --git a/dev/uart8250.cc b/dev/uart8250.cc
index 99355e28a..65bccee86 100644
--- a/dev/uart8250.cc
+++ b/dev/uart8250.cc
@@ -112,7 +112,7 @@ Uart8250::Uart8250(const string &name, SimConsole *c, MemoryController *mmu,
}
-Fault *
+Fault
Uart8250::read(MemReqPtr &req, uint8_t *data)
{
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
@@ -188,7 +188,7 @@ Uart8250::read(MemReqPtr &req, uint8_t *data)
}
-Fault *
+Fault
Uart8250::write(MemReqPtr &req, const uint8_t *data)
{
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
diff --git a/dev/uart8250.hh b/dev/uart8250.hh
index a0e2d344a..88abf8e24 100644
--- a/dev/uart8250.hh
+++ b/dev/uart8250.hh
@@ -82,8 +82,8 @@ class Uart8250 : public Uart
Addr a, Addr s, HierParams *hier, Bus *pio_bus, Tick pio_latency,
Platform *p);
- virtual Fault * read(MemReqPtr &req, uint8_t *data);
- virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault read(MemReqPtr &req, uint8_t *data);
+ virtual Fault write(MemReqPtr &req, const uint8_t *data);
/**
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 13:22:42 +0000