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-rw-r--r--ext/dsent/tech/tech_models/Bulk22LVT.model179
-rw-r--r--ext/dsent/tech/tech_models/Bulk32LVT.model168
-rw-r--r--ext/dsent/tech/tech_models/Bulk45LVT.model168
-rw-r--r--ext/dsent/tech/tech_models/Photonics.model89
-rw-r--r--ext/dsent/tech/tech_models/TG11LVT.model181
5 files changed, 785 insertions, 0 deletions
diff --git a/ext/dsent/tech/tech_models/Bulk22LVT.model b/ext/dsent/tech/tech_models/Bulk22LVT.model
new file mode 100644
index 000000000..e2087a12d
--- /dev/null
+++ b/ext/dsent/tech/tech_models/Bulk22LVT.model
@@ -0,0 +1,179 @@
+# WARNING: Most commercial fabs will not be happy if you release their exact
+# process information! If you derive these numbers through SPICE models,
+# the process design kit, or any other confidential material, please round-off
+# the values and leave the process name unidentifiable by fab (i.e. call it
+# Bulk90LVT instead of TSMC90LVT) if you release parameters publicly. This
+# rule may not apply for open processes, but you may want to check.
+
+# All units are in SI, (volts, meters, kelvin, farads, ohms, amps, etc.)
+
+# This file contains the model for a bulk 22nm LVT process
+Name = Bulk22LVT
+
+# Supply voltage used in the circuit and for characterizations (V)
+Vdd = 0.8
+# Temperature (K)
+Temperature = 340
+
+# =============================================================================
+# Parameters for transistors
+# =============================================================================
+
+# Contacted gate pitch (m)
+Gate->PitchContacted = 0.120e-6
+
+# Min gate width (m)
+Gate->MinWidth = 0.100e-6
+
+# Gate cap per unit width (F/m)
+Gate->CapPerWidth = 0.900e-9
+# Source/Drain cap per unit width (F/m)
+Drain->CapPerWidth = 0.620e-9
+
+# Parameters characterization temperature (K)
+Nmos->CharacterizedTemperature = 300.0
+Pmos->CharacterizedTemperature = 300.0
+
+#------------------------------------------------------------------------------
+# I_Eff definition in Na, IEDM 2002
+# I_EFF = (I(VG = 0.5, VD = 1.0) + I(VG = 1.0, VD = 0.5))/2
+# R_EFF = VDD / I_EFF * 1 / (2 ln(2))
+# This is generally accurate for when input and output transition times
+# are similar, which is a reasonable case after timing optimization
+#------------------------------------------------------------------------------
+# Effective resistance (Ohm-m)
+Nmos->EffResWidth = 0.700e-3
+Pmos->EffResWidth = 0.930e-3
+
+#------------------------------------------------------------------------------
+# The ratio of extra effective resistance with each additional stacked
+# transistor
+# EffResStackRatio = (R_EFF_NAND2 - R_EFF_INV) / R_EFF_INV)
+# For example, inverter has an normalized effective drive resistance of 1.0.
+# A NAND2 (2-stack) will have an effective drive of 1.0 + 0.7, a NAND3 (3-stack)
+# will have an effective drive of 1.0 + 2 * 0.7. Use NORs for Pmos. This fit
+# works relatively well up to 4 stacks. This value will change depending on the
+# VDD used.
+#------------------------------------------------------------------------------
+# Effective resistance stack ratio
+Nmos->EffResStackRatio = 0.800
+Pmos->EffResStackRatio = 0.680
+
+#------------------------------------------------------------------------------
+# I_OFF defined as |I_DS| for |V_DS| = V_DD and |V_GS| = 0.0
+# Minimum off current is used in technologies where I_OFF stops scaling
+# with transistor width below some threshold
+#------------------------------------------------------------------------------
+# Off current per width (A/m)
+Nmos->OffCurrent = 100.0e-3
+Pmos->OffCurrent = 100.0e-3
+# Minimum off current (A)
+Nmos->MinOffCurrent = 60e-9
+Pmos->MinOffCurrent = 60e-9
+
+# Subthreshold swing (V/dec)
+Nmos->SubthresholdSwing = 0.100
+Pmos->SubthresholdSwing = 0.100
+# DIBL factor (V/V)
+Nmos->DIBL = 0.150
+Pmos->DIBL = 0.150
+# Subthreshold temperature swing (K/dec)
+Nmos->SubthresholdTempSwing = 100.0
+Pmos->SubthresholdTempSwing = 100.0
+#------------------------------------------------------------------------------
+
+# =============================================================================
+# Parameters for interconnect
+# =============================================================================
+
+Wire->AvailableLayers = [Metal1,Local,Intermediate,Semiglobal,Global]
+
+# Metal 1 Wire (used for std cell routing only)
+# Min width (m)
+Wire->Metal1->MinWidth = 32e-9
+# Min spacing (m)
+Wire->Metal1->MinSpacing = 32e-9
+# Resistivity (Ohm-m)
+Wire->Metal1->Resistivity = 5.00e-8
+# Metal thickness (m)
+Wire->Metal1->MetalThickness = 60.0e-9
+# Dielectric thickness (m)
+Wire->Metal1->DielectricThickness = 60.0e-9
+# Dielectric constant
+Wire->Metal1->DielectricConstant = 3.00
+
+# Local wire, 1.0X of the M1 pitch
+# Min width (m)
+Wire->Local->MinWidth = 32e-9
+# Min spacing (m)
+Wire->Local->MinSpacing = 32e-9
+# Resistivity (Ohm-m)
+Wire->Local->Resistivity = 5.00e-8
+# Metal thickness (m)
+Wire->Local->MetalThickness = 60.0e-9
+# Dielectric thickness (m)
+Wire->Local->DielectricThickness = 60.0e-9
+# Dielectric constant
+Wire->Local->DielectricConstant = 3.00
+
+# Intermediate wire, 2.0X the M1 pitch
+# Min width (m)
+Wire->Intermediate->MinWidth = 55e-9
+# Min spacing (m)
+Wire->Intermediate->MinSpacing = 55e-9
+# Resistivity (Ohm-m)
+Wire->Intermediate->Resistivity = 4.00e-8
+# Metal thickness (m)
+Wire->Intermediate->MetalThickness = 100.0e-9
+# Dielectric thickness (m)
+Wire->Intermediate->DielectricThickness = 100.0e-9
+# Dielectric constant
+Wire->Intermediate->DielectricConstant = 2.8
+
+# Semiglobal wire, 4.0X the M1 pitch
+# Min width (m)
+Wire->Semiglobal->MinWidth = 110e-9
+# Min spacing (m)
+Wire->Semiglobal->MinSpacing = 110e-9
+# Resistivity (Ohm-m)
+Wire->Semiglobal->Resistivity = 2.60e-8
+# Metal thickness (m)
+Wire->Semiglobal->MetalThickness = 200e-9
+# Dielectric thickness (m)
+Wire->Semiglobal->DielectricThickness = 170e-9
+# Dielectric constant
+Wire->Semiglobal->DielectricConstant = 2.80
+
+# Global wire, 6.0X the M1 pitch
+# Min width (m)
+Wire->Global->MinWidth = 160e-9
+# Min spacing (m)
+Wire->Global->MinSpacing = 160e-9
+# Resistivity (Ohm-m)
+Wire->Global->Resistivity = 2.30e-8
+# Metal thickness (m)
+Wire->Global->MetalThickness = 280e-9
+# Dielectric thickness (m)
+Wire->Global->DielectricThickness = 250e-9
+# Dielectric constant
+Wire->Global->DielectricConstant = 2.60
+
+# =============================================================================
+# Parameters for Standard Cells
+# =============================================================================
+
+# The height of the standard cell is usually a multiple of the vertical
+# M1 pitch (tracks). By definition, an X1 size cell has transistors
+# that fit exactly in the given cell height without folding, or leaving
+# any wasted vertical area
+
+# Reasonable values for the number of M1 tracks that we have seen are 8-14
+StdCell->Tracks = 11
+# Height overhead due to supply rails, well spacing, etc. Note that this will grow
+# if the height of the standard cell decreases!
+StdCell->HeightOverheadFactor = 1.400
+
+# Sets the available sizes of each standard cell. Keep in mind that
+# 1.0 is the biggest cell without any transistor folding
+StdCell->AvailableSizes = [1.0, 1.4, 2.0, 3.0, 4.0, 6.0, 8.0, 10.0, 12.0, 16.0]
+
diff --git a/ext/dsent/tech/tech_models/Bulk32LVT.model b/ext/dsent/tech/tech_models/Bulk32LVT.model
new file mode 100644
index 000000000..9a90bdaf9
--- /dev/null
+++ b/ext/dsent/tech/tech_models/Bulk32LVT.model
@@ -0,0 +1,168 @@
+# WARNING: Most commercial fabs will not be happy if you release their exact
+# process information! If you derive these numbers through SPICE models,
+# the process design kit, or any other confidential material, please round-off
+# the values and leave the process name unidentifiable by fab (i.e. call it
+# Bulk90LVT instead of TSMC90LVT) if you release parameters publicly. This
+# rule may not apply for open processes, but you may want to check.
+
+# All units are in SI, (volts, meters, kelvin, farads, ohms, amps, etc.)
+
+# This file contains the model for a bulk 32nm LVT process
+Name = Bulk32LVT
+
+# Supply voltage used in the circuit and for characterizations (V)
+Vdd = 0.9
+# Temperature (K)
+Temperature = 340
+
+# =============================================================================
+# Parameters for transistors
+# =============================================================================
+
+# Contacted gate pitch (m)
+Gate->PitchContacted = 0.160e-6
+
+# Min gate width (m)
+Gate->MinWidth = 0.120e-6
+
+# Gate cap per unit width (F/m)
+Gate->CapPerWidth = 0.950e-9
+# Source/Drain cap per unit width (F/m)
+Drain->CapPerWidth = 0.640e-9
+
+# Parameters characterization temperature (K)
+Nmos->CharacterizedTemperature = 300.0
+Pmos->CharacterizedTemperature = 300.0
+
+#------------------------------------------------------------------------------
+# I_Eff definition in Na, IEDM 2002
+# I_EFF = (I(VG = 0.5, VD = 1.0) + I(VG = 1.0, VD = 0.5))/2
+# R_EFF = VDD / I_EFF * 1 / (2 ln(2))
+# This is generally accurate for when input and output transition times
+# are similar, which is a reasonable case after timing optimization
+#------------------------------------------------------------------------------
+# Effective resistance (Ohm-m)
+Nmos->EffResWidth = 0.890e-3
+Pmos->EffResWidth = 1.270e-3
+
+#------------------------------------------------------------------------------
+# The ratio of extra effective resistance with each additional stacked
+# transistor
+# EffResStackRatio = (R_EFF_NAND2 - R_EFF_INV) / R_EFF_INV)
+# For example, inverter has an normalized effective drive resistance of 1.0.
+# A NAND2 (2-stack) will have an effective drive of 1.0 + 0.7, a NAND3 (3-stack)
+# will have an effective drive of 1.0 + 2 * 0.7. Use NORs for Pmos. This fit
+# works relatively well up to 4 stacks. This value will change depending on the
+# VDD used.
+#------------------------------------------------------------------------------
+# Effective resistance stack ratio
+Nmos->EffResStackRatio = 0.78
+Pmos->EffResStackRatio = 0.66
+
+#------------------------------------------------------------------------------
+# I_OFF defined as |I_DS| for |V_DS| = V_DD and |V_GS| = 0.0
+# Minimum off current is used as a second fit point, since I_OFF often
+# stops scaling with transistor width below some threshold
+#------------------------------------------------------------------------------
+# Off current per width (A/m)
+Nmos->OffCurrent = 100e-3
+Pmos->OffCurrent = 100e-3
+
+# Minimum off current (A)
+Nmos->MinOffCurrent = 100e-9
+Pmos->MinOffCurrent = 20e-9
+
+# Subthreshold swing (V/dec)
+Nmos->SubthresholdSwing = 0.100
+Pmos->SubthresholdSwing = 0.100
+
+# DIBL factor (V/V)
+Nmos->DIBL = 0.150
+Pmos->DIBL = 0.150
+
+# Subthreshold leakage temperature swing (K/dec)
+Nmos->SubthresholdTempSwing = 100
+Pmos->SubthresholdTempSwing = 100
+#------------------------------------------------------------------------------
+
+# =============================================================================
+# Parameters for interconnect
+# =============================================================================
+
+Wire->AvailableLayers = [Metal1,Local,Intermediate,Global]
+
+# Metal 1 Wire (used for std cell routing only)
+# Min width (m)
+Wire->Metal1->MinWidth = 55e-9
+# Min spacing (m)
+Wire->Metal1->MinSpacing = 55e-9
+# Resistivity (Ohm-m)
+Wire->Metal1->Resistivity = 4.00e-8
+# Metal thickness (m)
+Wire->Metal1->MetalThickness = 100.0e-9
+# Dielectric thickness (m)
+Wire->Metal1->DielectricThickness = 100.0e-9
+# Dielectric constant
+Wire->Metal1->DielectricConstant = 3.2
+
+# Local wire, 1.0X of the M1 pitch
+# Min width (m)
+Wire->Local->MinWidth = 55e-9
+# Min spacing (m)
+Wire->Local->MinSpacing = 55e-9
+# Resistivity (Ohm-m)
+Wire->Local->Resistivity = 4.00e-8
+# Metal thickness (m)
+Wire->Local->MetalThickness = 100.0e-9
+# Dielectric thickness (m)
+Wire->Local->DielectricThickness = 100.0e-9
+# Dielectric constant
+Wire->Local->DielectricConstant = 3.2
+
+# Intermediate wire, 2.0X the M1 pitch
+# Min width (m)
+Wire->Intermediate->MinWidth = 110e-9
+# Min spacing (m)
+Wire->Intermediate->MinSpacing = 110e-9
+# Resistivity (Ohm-m)
+Wire->Intermediate->Resistivity = 2.60e-8
+# Metal thickness (m)
+Wire->Intermediate->MetalThickness = 200e-9
+# Dielectric thickness (m)
+Wire->Intermediate->DielectricThickness = 170e-9
+# Dielectric constant
+Wire->Intermediate->DielectricConstant = 3.00
+
+# Global wire, 3.0X the M1 pitch
+# Min width (m)
+Wire->Global->MinWidth = 160e-9
+# Min spacing (m)
+Wire->Global->MinSpacing = 160e-9
+# Resistivity (Ohm-m)
+Wire->Global->Resistivity = 2.30e-8
+# Metal thickness (m)
+Wire->Global->MetalThickness = 280e-9
+# Dielectric thickness (m)
+Wire->Global->DielectricThickness = 250e-9
+# Dielectric constant
+Wire->Global->DielectricConstant = 2.80
+
+# =============================================================================
+# Parameters for Standard Cells
+# =============================================================================
+
+# The height of the standard cell is usually a multiple of the vertical
+# M1 pitch (tracks). By definition, an X1 size cell has transistors
+# that fit exactly in the given cell height without folding, or leaving
+# any wasted vertical area
+
+# Reasonable values for the number of M1 tracks that we have seen are 8-14
+StdCell->Tracks = 11
+# Height overhead due to supply rails, well spacing, etc. Note that this will grow
+# if the height of the standard cell decreases!
+StdCell->HeightOverheadFactor = 1.400
+
+# Sets the available sizes of each standard cell. Keep in mind that
+# 1.0 is the biggest cell without any transistor folding
+StdCell->AvailableSizes = [1.0, 1.4, 2.0, 3.0, 4.0, 6.0, 8.0, 10.0, 12.0, 16.0]
+
diff --git a/ext/dsent/tech/tech_models/Bulk45LVT.model b/ext/dsent/tech/tech_models/Bulk45LVT.model
new file mode 100644
index 000000000..d8015c522
--- /dev/null
+++ b/ext/dsent/tech/tech_models/Bulk45LVT.model
@@ -0,0 +1,168 @@
+# WARNING: Most commercial fabs will not be happy if you release their exact
+# process information! If you derive these numbers through SPICE models,
+# the process design kit, or any other confidential material, please round-off
+# the values and leave the process name unidentifiable by fab (i.e. call it
+# Bulk90LVT instead of TSMC90LVT) if you release parameters publicly. This
+# rule may not apply for open processes, but you may want to check.
+
+# All units are in SI, (volts, meters, kelvin, farads, ohms, amps, etc.)
+
+# This file contains the model for a bulk 45nm LVT process
+Name = Bulk45LVT
+
+# Supply voltage used in the circuit and for characterizations (V)
+Vdd = 1.0
+# Temperature (K)
+Temperature = 340
+
+# =============================================================================
+# Parameters for transistors
+# =============================================================================
+
+# Contacted gate pitch (m)
+Gate->PitchContacted = 0.200e-6
+
+# Min gate width (m)
+Gate->MinWidth = 0.160e-6
+
+# Gate cap per unit width (F/m)
+Gate->CapPerWidth = 1.000e-9
+# Source/Drain cap per unit width (F/m)
+Drain->CapPerWidth = 0.600e-9
+
+# Parameters characterization temperature (K)
+Nmos->CharacterizedTemperature = 300.0
+Pmos->CharacterizedTemperature = 300.0
+
+#------------------------------------------------------------------------------
+# I_Eff definition in Na, IEDM 2002
+# I_EFF = (I(VG = 0.5, VD = 1.0) + I(VG = 1.0, VD = 0.5))/2
+# R_EFF = VDD / I_EFF * 1 / (2 ln(2))
+# This is generally accurate for when input and output transition times
+# are similar, which is a reasonable case after timing optimization
+#------------------------------------------------------------------------------
+# Effective resistance (Ohm-m)
+Nmos->EffResWidth = 1.100e-3
+Pmos->EffResWidth = 1.500e-3
+
+#------------------------------------------------------------------------------
+# The ratio of extra effective resistance with each additional stacked
+# transistor
+# EffResStackRatio = (R_EFF_NAND2 - R_EFF_INV) / R_EFF_INV)
+# For example, inverter has an normalized effective drive resistance of 1.0.
+# A NAND2 (2-stack) will have an effective drive of 1.0 + 0.7, a NAND3 (3-stack)
+# will have an effective drive of 1.0 + 2 * 0.7. Use NORs for Pmos. This fit
+# works relatively well up to 4 stacks. This value will change depending on the
+# VDD used.
+#------------------------------------------------------------------------------
+# Effective resistance stack ratio
+Nmos->EffResStackRatio = 0.7
+Pmos->EffResStackRatio = 0.6
+
+#------------------------------------------------------------------------------
+# I_OFF defined as |I_DS| for |V_DS| = V_DD and |V_GS| = 0.0
+# Minimum off current is used as a second fit point, since I_OFF often
+# stops scaling with transistor width below some threshold
+#------------------------------------------------------------------------------
+# Off current per width (A/m)
+Nmos->OffCurrent = 100e-3
+Pmos->OffCurrent = 100e-3
+
+# Minimum off current (A)
+Nmos->MinOffCurrent = 100e-9
+Pmos->MinOffCurrent = 20e-9
+
+# Subthreshold swing (V/dec)
+Nmos->SubthresholdSwing = 0.100
+Pmos->SubthresholdSwing = 0.100
+
+# DIBL factor (V/V)
+Nmos->DIBL = 0.150
+Pmos->DIBL = 0.150
+
+# Subthreshold leakage temperature swing (K/dec)
+Nmos->SubthresholdTempSwing = 100
+Pmos->SubthresholdTempSwing = 100
+#------------------------------------------------------------------------------
+
+# =============================================================================
+# Parameters for interconnect
+# =============================================================================
+
+Wire->AvailableLayers = [Metal1,Local,Intermediate,Global]
+
+# Metal 1 Wire (used for std cell routing only)
+# Min width (m)
+Wire->Metal1->MinWidth = 80e-9
+# Min spacing (m)
+Wire->Metal1->MinSpacing = 80e-9
+# Resistivity (Ohm-m)
+Wire->Metal1->Resistivity = 3.00e-8
+# Metal thickness (m)
+Wire->Metal1->MetalThickness = 140.0e-9
+# Dielectric thickness (m)
+Wire->Metal1->DielectricThickness = 130.0e-9
+# Dielectric constant
+Wire->Metal1->DielectricConstant = 3.2
+
+# Local wire, 1.0X of the M1 pitch
+# Min width (m)
+Wire->Metal1->MinWidth = 80e-9
+# Min spacing (m)
+Wire->Metal1->MinSpacing = 80e-9
+# Resistivity (Ohm-m)
+Wire->Metal1->Resistivity = 3.00e-8
+# Metal thickness (m)
+Wire->Metal1->MetalThickness = 140.0e-9
+# Dielectric thickness (m)
+Wire->Metal1->DielectricThickness = 130.0e-9
+# Dielectric constant
+Wire->Metal1->DielectricConstant = 3.2
+
+# Intermediate wire, 1.4X the M1 pitch
+# Min width (m)
+Wire->Intermediate->MinWidth = 110e-9
+# Min spacing (m)
+Wire->Intermediate->MinSpacing = 110e-9
+# Resistivity (Ohm-m)
+Wire->Intermediate->Resistivity = 2.60e-8
+# Metal thickness (m)
+Wire->Intermediate->MetalThickness = 200e-9
+# Dielectric thickness (m)
+Wire->Intermediate->DielectricThickness = 170e-9
+# Dielectric constant
+Wire->Intermediate->DielectricConstant = 3.00
+
+# Global wire, 2.0X the M1 pitch
+# Min width (m)
+Wire->Global->MinWidth = 160e-9
+# Min spacing (m)
+Wire->Global->MinSpacing = 160e-9
+# Resistivity (Ohm-m)
+Wire->Global->Resistivity = 2.30e-8
+# Metal thickness (m)
+Wire->Global->MetalThickness = 280e-9
+# Dielectric thickness (m)
+Wire->Global->DielectricThickness = 250e-9
+# Dielectric constant
+Wire->Global->DielectricConstant = 2.80
+
+# =============================================================================
+# Parameters for Standard Cells
+# =============================================================================
+
+# The height of the standard cell is usually a multiple of the vertical
+# M1 pitch (tracks). By definition, an X1 size cell has transistors
+# that fit exactly in the given cell height without folding, or leaving
+# any wasted vertical area
+
+# Reasonable values for the number of M1 tracks that we have seen are 8-14
+StdCell->Tracks = 11
+# Height overhead due to supply rails, well spacing, etc. Note that this will grow
+# if the height of the standard cell decreases!
+StdCell->HeightOverheadFactor = 1.400
+
+# Sets the available sizes of each standard cell. Keep in mind that
+# 1.0 is the biggest cell without any transistor folding
+StdCell->AvailableSizes = [1.0, 1.4, 2.0, 3.0, 4.0, 6.0, 8.0, 10.0, 12.0, 16.0]
+
diff --git a/ext/dsent/tech/tech_models/Photonics.model b/ext/dsent/tech/tech_models/Photonics.model
new file mode 100644
index 000000000..335e1e832
--- /dev/null
+++ b/ext/dsent/tech/tech_models/Photonics.model
@@ -0,0 +1,89 @@
+# This file contains the model for photonic devices/circuits
+PhotonicsName = Photonics
+
+# ALL PARAMETERS IN SI UNITS!!! (J, W, m, F, dB, A)
+
+# -----------------------------------------------------------------------------
+# Waveguide
+# -----------------------------------------------------------------------------
+Waveguide->LossPerMeter = 100 # dB/m
+Waveguide->Pitch = 4e-6 # m
+Splitter->Loss = 1.00 # dB
+Coupler->Loss = 1.00 # dB
+
+# -----------------------------------------------------------------------------
+# Laser
+# -----------------------------------------------------------------------------
+
+# Continuous wave off-chip (always on) laser
+Laser->CW->Efficiency = 0.25 # P_Laser/P_Electrical
+Laser->CW->LaserDiodeLoss = 1.00 # Laser diode loss
+Laser->CW->Area = 0
+
+# Gated on-chip (data-dependent) laser
+Laser->GatedCW->Efficiency = 0.25 # P_Laser/P_Electrical
+Laser->GatedCW->LaserDiodeLoss = 1.00 # Laser diode loss
+Laser->GatedCW->Area = 200e-12
+
+# -----------------------------------------------------------------------------
+# Modulators
+# -----------------------------------------------------------------------------
+# Ring Modulator
+Modulator->Ring->SupplyBoostRatio = 1.2 # Boost the supply voltage above required reverse bias voltage by this ratio
+Modulator->Ring->ParasiticRes = 100 # ohm
+Modulator->Ring->ParasiticCap = 5e-15 # F
+Modulator->Ring->FCPDEffect = 3e-27 # Free carrier plasma dispersion effect, delta_n/delta_c (m^-3)
+Modulator->Ring->Tn = 0.01 # Transmisivity at the bottom of the notch
+Modulator->Ring->NA = 3e24 # m^3, p doping
+Modulator->Ring->ND = 1e24 # m^3, n doping
+Modulator->Ring->ni = 1e16 # m^3, intrinsic free carriers
+Modulator->Ring->JunctionRatio = 0.8 # Junction ratio to total optical length
+Modulator->Ring->Height = 500e-9 # Height of the junction (m)
+Modulator->Ring->Width = 500e-9 # Modulator width (m)
+Modulator->Ring->ConfinementFactor = 0.3 # Modulator confinement factor
+
+# -----------------------------------------------------------------------------
+# Ring Resonator
+# -----------------------------------------------------------------------------
+Ring->Area = 100e-12 # m2
+Ring->Lambda = 1300e-9 # Resonant wavelength range
+Ring->GroupIndex = 4 # Group index
+Ring->Radius = 3e-6 # Bend radius of the ring
+Ring->ConfinementFactor = 0.3 # Confinement factor
+Ring->ThroughLoss = 0.01 # [dB]
+Ring->DropLoss = 1.0 # [dB]
+Ring->MaxQualityFactor = 150e3 # Maximum quality factor
+Ring->HeatingEfficiency = 100000 # Ring heating efficiency [K/W]
+Ring->TuningEfficiency = 10e9 # Ring tuning efficiency [Hz/K]
+Ring->LocalVariationSigma = 40e9 # Ring resonance frequency local mismatch sigma [Hz]
+Ring->SystematicVariationSigma = 200e9 # Ring resonance frequency systematic mismatch sigma [Hz]
+Ring->TemperatureMax = 380 # Maximum temperature that the tuning mechanism must still be able to work at [K]
+Ring->TemperatureMin = 280 # Minimum temperature that the tuning mechanism must still be able to work at [K]
+Ring->MaxElectricallyTunableFreq = 50e9 # Maximum electrically tunable range when allowing for electrically assisted tuning [Hz]
+
+# -----------------------------------------------------------------------------
+# Photodetector
+# -----------------------------------------------------------------------------
+Photodetector->Responsivity = 1.1 #(A/W)
+Photodetector->Area = 10e-12 # m2
+Photodetector->Cap = 0 # F
+Photodetector->ParasiticCap = 5e-15 # F
+Photodetector->Loss = 1.00 # dB
+Photodetector->MinExtinctionRatio = 3 # dB
+Photodetector->AvalancheGain = 1 # avalanche gain
+
+# -----------------------------------------------------------------------------
+# Receivers
+# -----------------------------------------------------------------------------
+
+# Sense amplifier (common to all receivers)
+SenseAmp->BER = 1e-15 # Target bit error rate
+SenseAmp->CMRR = 5 # Common-mode rejection ratio
+SenseAmp->OffsetCompensationBits = 5 # Number of bits used for fine-tuning offset compensation
+SenseAmp->OffsetRatio = 0.04 # Offset mismatch (as a fraction of VDD)
+SenseAmp->SupplyNoiseRandRatio = 0.01 # Random supply noise (as a fraction VDD)
+SenseAmp->SupplyNoiseDetRatio = 0.05 # Deterministic supply noise (as a fraction VDD)
+SenseAmp->NoiseMargin = 0.02 # Extra noise margin
+SenseAmp->JitterRatio = 0.01 # Jitter (as a fraction of Tbit)
+
+Receiver->Int->IntegrationTimeRatio = 0.7 # Integration time (as a fraction of Tbit)
diff --git a/ext/dsent/tech/tech_models/TG11LVT.model b/ext/dsent/tech/tech_models/TG11LVT.model
new file mode 100644
index 000000000..292e40ab0
--- /dev/null
+++ b/ext/dsent/tech/tech_models/TG11LVT.model
@@ -0,0 +1,181 @@
+# WARNING: Most commercial fabs will not be happy if you release their exact
+# process information! If you derive these numbers through SPICE models,
+# the process design kit, or any other confidential material, please round-off
+# the values and leave the process name unidentifiable by fab (i.e. call it
+# Bulk90LVT instead of TSMC90LVT) if you release parameters publicly. This
+# rule may not apply for open processes, but you may want to check.
+
+# All units are in SI, (volts, meters, kelvin, farads, ohms, amps, etc.)
+
+# This file contains the model for a Tri-Gate (Multi-Gate) 11nm LVT process
+Name = TG11LVT
+
+# Supply voltage used in the circuit and for characterizations (V)
+Vdd = 0.6
+# Temperature (K)
+Temperature = 340
+
+# =============================================================================
+# Parameters for transistors
+# =============================================================================
+
+# Contacted gate pitch (m)
+Gate->PitchContacted = 0.080e-6
+
+# Min gate width (m)
+Gate->MinWidth = 0.080e-6
+
+# Gate cap per unit width (F/m)
+Gate->CapPerWidth = 0.61e-9
+# Source/Drain cap per unit width (F/m)
+Drain->CapPerWidth = 0.56e-9
+
+# Parameters characterization temperature (K)
+Nmos->CharacterizedTemperature = 300.0
+Pmos->CharacterizedTemperature = 300.0
+
+#------------------------------------------------------------------------------
+# I_Eff definition in Na, IEDM 2002
+# I_EFF = (I(VG = 0.5, VD = 1.0) + I(VG = 1.0, VD = 0.5))/2
+# R_EFF = VDD / I_EFF * 1 / (2 ln(2))
+# This is generally more accurate for when the delay is input transition time
+# limited
+#------------------------------------------------------------------------------
+# Effective resistance (Ohm-m)
+Nmos->EffResWidth = 1.16e-3
+Pmos->EffResWidth = 1.28e-3
+
+#------------------------------------------------------------------------------
+# The ratio of extra effective resistance with each additional stacked
+# transistor
+# EffResStackRatio = (R_EFF_NAND2 - R_EFF_INV) / R_EFF_INV)
+# For example, inverter has an normalized effective drive resistance of 1.0.
+# A NAND2 (2-stack) will have an effective drive of 1.0 + 0.7, a NAND3 (3-stack)
+# will have an effective drive of 1.0 + 2 * 0.7. Use NORs for Pmos. This fit
+# works relatively well up to 4 stacks. This value will change depending on the
+# VDD used.
+#------------------------------------------------------------------------------
+# Effective resistance stack ratio
+Nmos->EffResStackRatio = 0.89
+Pmos->EffResStackRatio = 0.86
+
+#------------------------------------------------------------------------------
+# I_OFF defined as |I_DS| for |V_DS| = V_DD and |V_GS| = 0.0
+# Minimum off current is used in technologies where I_OFF stops scaling
+# with transistor width below some threshold
+#------------------------------------------------------------------------------
+# Off current per width (A/m)
+Nmos->OffCurrent = 100.0e-3
+Pmos->OffCurrent = 100.0e-3
+# Minimum off current (A)
+Nmos->MinOffCurrent = 40e-9
+Pmos->MinOffCurrent = 4e-9
+
+# Subthreshold swing (V/dec)
+Nmos->SubthresholdSwing = 0.080
+Pmos->SubthresholdSwing = 0.080
+# DIBL factor (V/V)
+Nmos->DIBL = 0.125
+Pmos->DIBL = 0.125
+# Subthreshold temperature swing (K/dec)
+Nmos->SubthresholdTempSwing = 100.0
+Pmos->SubthresholdTempSwing = 100.0
+#------------------------------------------------------------------------------
+
+# =============================================================================
+# Parameters for interconnect
+# =============================================================================
+
+Wire->AvailableLayers = [Metal1,Local,Intermediate,Semiglobal,Global]
+
+# Metal 1 Wire (used for std cell routing only)
+# Min width (m)
+Wire->Metal1->MinWidth = 20e-9
+# Min spacing (m)
+Wire->Metal1->MinSpacing = 20e-9
+# Resistivity (Ohm-m)
+Wire->Metal1->Resistivity = 6.8e-8
+# Metal thickness (m)
+Wire->Metal1->MetalThickness = 35.0e-9
+# Dielectric thickness (m)
+Wire->Metal1->DielectricThickness = 35.0e-9
+# Dielectric constant
+Wire->Metal1->DielectricConstant = 3.00
+
+# Local wire, 1.0X of the M1 pitch
+# Min width (m)
+Wire->Local->MinWidth = 20e-9
+# Min spacing (m)
+Wire->Local->MinSpacing = 20e-9
+# Resistivity (Ohm-m)
+Wire->Local->Resistivity = 6.8e-8
+# Metal thickness (m)
+Wire->Local->MetalThickness = 35.0e-9
+# Dielectric thickness (m)
+Wire->Local->DielectricThickness = 35.0e-9
+# Dielectric constant
+Wire->Local->DielectricConstant = 3.00
+
+# Intermediate wire, 2.0X the M1 pitch
+# Min width (m)
+Wire->Intermediate->MinWidth = 40e-9
+# Min spacing (m)
+Wire->Intermediate->MinSpacing = 40e-9
+# Resistivity (Ohm-m)
+Wire->Intermediate->Resistivity = 4.50e-8
+# Metal thickness (m)
+Wire->Intermediate->MetalThickness = 70.0e-9
+# Dielectric thickness (m)
+Wire->Intermediate->DielectricThickness = 70.0e-9
+# Dielectric constant
+Wire->Intermediate->DielectricConstant = 2.80
+
+# Semiglobal wire, 4.0X the M1 pitch
+# Min width (m)
+Wire->Semiglobal->MinWidth = 80e-9
+# Min spacing (m)
+Wire->Semiglobal->MinSpacing = 80e-9
+# Resistivity (Ohm-m)
+Wire->Semiglobal->Resistivity = 2.80e-8
+# Metal thickness (m)
+Wire->Semiglobal->MetalThickness = 150.0e-9
+# Dielectric thickness (m)
+Wire->Semiglobal->DielectricThickness = 150.0e-9
+# Dielectric constant
+Wire->Semiglobal->DielectricConstant = 2.60
+
+# Global wire, 8.0X the M1 pitch
+# Min width (m)
+Wire->Global->MinWidth = 160e-9
+# Min spacing (m)
+Wire->Global->MinSpacing = 160e-9
+# Resistivity (Ohm-m)
+Wire->Global->Resistivity = 2.30e-8
+# Metal thickness (m)
+Wire->Global->MetalThickness = 280e-9
+# Dielectric thickness (m)
+Wire->Global->DielectricThickness = 250e-9
+# Dielectric constant
+Wire->Global->DielectricConstant = 2.60
+
+# =============================================================================
+# Parameters for Standard Cells
+# =============================================================================
+
+# The height of the standard cell is usually a multiple of the vertical
+# M1 pitch (tracks). By definition, an X1 size cell has transistors
+# that fit exactly in the given cell height without folding, or leaving
+# any wasted vertical area
+
+# Reasonable values for the number of M1 tracks that we have seen are 8-14
+StdCell->Tracks = 11
+# Height overhead due to supply rails, well spacing, etc. Note that this will grow
+# if the height of the standard cell decreases!
+StdCell->HeightOverheadFactor = 1.400
+
+# Sets the available sizes of each standard cell. Keep in mind that
+# 1.0 is the biggest cell without any transistor folding
+StdCell->AvailableSizes = [1.0, 1.4, 2.0, 3.0, 4.0, 6.0, 8.0, 10.0, 12.0, 16.0]
+
+
+
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