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-rw-r--r--ext/dsent/tech/TechModel.cc320
-rw-r--r--ext/dsent/tech/TechModel.h71
-rw-r--r--ext/dsent/tech/tech_models/Bulk22LVT.model179
-rw-r--r--ext/dsent/tech/tech_models/Bulk32LVT.model168
-rw-r--r--ext/dsent/tech/tech_models/Bulk45LVT.model168
-rw-r--r--ext/dsent/tech/tech_models/Photonics.model89
-rw-r--r--ext/dsent/tech/tech_models/TG11LVT.model181
7 files changed, 1176 insertions, 0 deletions
diff --git a/ext/dsent/tech/TechModel.cc b/ext/dsent/tech/TechModel.cc
new file mode 100644
index 000000000..5922177ad
--- /dev/null
+++ b/ext/dsent/tech/TechModel.cc
@@ -0,0 +1,320 @@
+#include "tech/TechModel.h"
+
+#include <cmath>
+
+#include "model/std_cells/StdCellLib.h"
+
+namespace DSENT
+{
+ TechModel::TechModel()
+ : Config(), m_std_cell_lib_(NULL), m_available_wire_layers_(NULL)
+ {}
+
+ TechModel::~TechModel()
+ {}
+
+ void TechModel::setStdCellLib(const StdCellLib* std_cell_lib_)
+ {
+ m_std_cell_lib_ = std_cell_lib_;
+ return;
+ }
+
+ const StdCellLib* TechModel::getStdCellLib() const
+ {
+ return m_std_cell_lib_;
+ }
+
+ TechModel* TechModel::clone() const
+ {
+ return new TechModel(*this);
+ }
+
+ void TechModel::readFile(const String& filename_)
+ {
+ // Read the main technology file
+ LibUtil::Config::readFile(filename_);
+
+ // Search for "INCLUDE" to include more technology files
+ StringMap::ConstIterator it;
+ for(it = begin(); it != end(); ++it)
+ {
+ const String& key = it->first;
+ if(key.compare(0, 8, "INCLUDE_") == 0)
+ {
+ const String& include_filename = it->second;
+ LibUtil::Config::readFile(include_filename);
+ }
+ }
+
+ // Set the available wire layers
+ const vector<String>& available_wire_layer_vector = get("Wire->AvailableLayers").split("[,]");
+ m_available_wire_layers_ = new std::set<String>;
+ for(unsigned int i = 0; i < available_wire_layer_vector.size(); ++i)
+ {
+ m_available_wire_layers_->insert(available_wire_layer_vector[i]);
+ }
+ return;
+ }
+
+ //-------------------------------------------------------------------------
+ // Transistor Related Functions
+ //-------------------------------------------------------------------------
+ //Returns the leakage current of NMOS transistors, given the transistor stakcing, transistor widths, and input combination
+ double TechModel::calculateNmosLeakageCurrent(unsigned int num_stacks_, double uni_stacked_mos_width_, unsigned int input_vector_) const
+ {
+ vector<double> stacked_mos_widths_(num_stacks_, uni_stacked_mos_width_);
+ return calculateNmosLeakageCurrent(num_stacks_, stacked_mos_widths_, input_vector_);
+ }
+
+ //Returns the leakage current of NMOS transistors, given the transistor stakcing, transistor widths, and input combination
+ double TechModel::calculateNmosLeakageCurrent(unsigned int num_stacks_, const vector<double>& stacked_mos_widths_, unsigned int input_vector_) const
+ {
+ // Get technology parameters
+ double vdd = get("Vdd");
+ double temp = get("Temperature");
+ double char_temp = get("Nmos->CharacterizedTemperature");
+ double min_off_current = get("Nmos->MinOffCurrent");
+ double off_current = get("Nmos->OffCurrent");
+ double subthreshold_swing = get("Nmos->SubthresholdSwing");
+ double dibl = get("Nmos->DIBL");
+ double temp_swing = get("Nmos->SubthresholdTempSwing");
+
+ // Map dibl to a swing value for easier calculation
+ double dibl_swing = subthreshold_swing / dibl;
+
+ //Calculate the leakage current factor
+ double leakage_current_factor = calculateLeakageCurrentFactor(num_stacks_, stacked_mos_widths_, input_vector_, vdd, subthreshold_swing, dibl_swing);
+
+ // Calcualte actual leakage current at characterized temperature
+ double leakage_current_char_tmp = stacked_mos_widths_[0] * off_current * std::pow(10.0, leakage_current_factor);
+ leakage_current_char_tmp = std::max(min_off_current, leakage_current_char_tmp);
+
+ // Calculate actual leakage current at temp
+ double leakage_current = leakage_current_char_tmp * std::pow(10.0, (temp - char_temp) / temp_swing);
+
+ return leakage_current;
+ }
+
+ double TechModel::calculatePmosLeakageCurrent(unsigned int num_stacks_, double uni_stacked_mos_width_, unsigned int input_vector_) const
+ {
+ vector<double> stacked_mos_widths_(num_stacks_, uni_stacked_mos_width_);
+ return calculatePmosLeakageCurrent(num_stacks_, stacked_mos_widths_, input_vector_);
+ }
+
+ //Returns the leakage current of PMOS transistors, given the transistor stakcing, transistor widths, and input combination
+ double TechModel::calculatePmosLeakageCurrent(unsigned int num_stacks_, const vector<double>& stacked_mos_widths_, unsigned int input_vector_) const
+ {
+ // Get technology parameters
+ double vdd = get("Vdd");
+ double temp = get("Temperature");
+ double char_temp = get("Pmos->CharacterizedTemperature");
+ double min_off_current = get("Pmos->MinOffCurrent");
+ double off_current = get("Pmos->OffCurrent");
+ double dibl = get("Pmos->DIBL");
+ double subthreshold_swing = get("Pmos->SubthresholdSwing");
+ double temp_swing = get("Nmos->SubthresholdTempSwing");
+
+ // Map dibl to a swing value for easier calculation
+ double dibl_swing = subthreshold_swing / dibl;
+
+ //Calculate the leakage current factor
+ double leakage_current_factor = calculateLeakageCurrentFactor(num_stacks_, stacked_mos_widths_, input_vector_, vdd, subthreshold_swing, dibl_swing);
+
+ // Calcualte actual leakage current at characterized temperature
+ double leakage_current_char_tmp = stacked_mos_widths_[0] * off_current * std::pow(10.0, leakage_current_factor);
+ leakage_current_char_tmp = std::max(min_off_current, leakage_current_char_tmp);
+
+ // Calculate actual leakage current at temp
+ double leakage_current = leakage_current_char_tmp * std::pow(10.0, (temp - char_temp) / temp_swing);
+
+ return leakage_current;
+ }
+
+ //Returns the leakage current, given the transistor stakcing, transistor widths, input combination,
+ //and technology information (vdd, subthreshold swing, subthreshold dibl swing)
+ double TechModel::calculateLeakageCurrentFactor(unsigned int num_stacks_, const vector<double>& stacked_mos_widths_, unsigned int input_vector_, double vdd_, double subthreshold_swing_, double dibl_swing_) const
+ {
+ // check everything is valid
+ ASSERT(num_stacks_ >= 1, "[Error] Number of stacks must be >= 1!");
+ ASSERT(stacked_mos_widths_.size() == num_stacks_, "[Error] Mismatch in number of stacks and the widths specified!");
+
+ //Use short name in this method
+ const double s1 = subthreshold_swing_;
+ const double s2 = dibl_swing_;
+
+ // Decode input combinations from input_vector_
+ std::vector<double> vs(num_stacks_, 0.0);
+ for(int i = 0; i < (int)num_stacks_; ++i)
+ {
+ double current_input = (double(input_vector_ & 0x1))*vdd_;
+ vs[i] = (current_input);
+ input_vector_ >>= 1;
+ }
+ // If the widths pointer is NULL, width is set to 1 by default
+ vector<double> ws = stacked_mos_widths_;
+
+ //Solve voltages at internal nodes of stacked transistors
+ // v[0] = 0
+ // v[num_stacks_] = vdd_
+ // v[i] = (1.0/(2*s1 + s2))*((s1 + s2)*v[i - 1] + s1*v[i + 1]
+ // + s2*(vs[i + 1] - vs[i]) + s1*s2*log10(ws[i + 1]/ws[i]))
+ //Use tri-matrix solver to solve the above linear system
+
+ double A = -(s1 + s2);
+ double B = 2*s1 + s2;
+ double C = -s1;
+ std::vector<double> a(num_stacks_ - 1, 0);
+ std::vector<double> b(num_stacks_ - 1, 0);
+ std::vector<double> c(num_stacks_ - 1, 0);
+ std::vector<double> d(num_stacks_ - 1, 0);
+ std::vector<double> v(num_stacks_ + 1, 0);
+ unsigned int eff_num_stacks = num_stacks_;
+ bool is_found_valid_v = false;
+ do
+ {
+ //Set boundary condition
+ v[0] = 0;
+ v[eff_num_stacks] = vdd_;
+
+ //If the effective number of stacks is 1, no matrix needs to be solved
+ if(eff_num_stacks == 1)
+ {
+ break;
+ }
+
+ //----------------------------------------------------------------------
+ //Setup the tri-matrix
+ //----------------------------------------------------------------------
+ for(int i = 0; i < (int)eff_num_stacks-2; ++i)
+ {
+ a[i + 1] = A;
+ c[i] = C;
+ }
+ for(int i = 0; i < (int)eff_num_stacks-1; ++i)
+ {
+ b[i] = B;
+ d[i] = s2*(vs[i + 1] - vs[i]) + s1*s2*std::log10(ws[i + 1]/ws[i]);
+ if(i == ((int)eff_num_stacks - 2))
+ {
+ d[i] -= C*vdd_;
+ }
+ }
+ //----------------------------------------------------------------------
+
+ //----------------------------------------------------------------------
+ //Solve the tri-matrix
+ //----------------------------------------------------------------------
+ for(int i = 1; i < (int)eff_num_stacks-1; ++i)
+ {
+ double m = a[i]/b[i - 1];
+ b[i] -= m*c[i - 1];
+ d[i] -= m*d[i - 1];
+ }
+
+ v[eff_num_stacks - 1] = d[eff_num_stacks - 2]/b[eff_num_stacks - 2];
+ for(int i = eff_num_stacks - 3; i >= 0; --i)
+ {
+ v[i + 1] = (d[i] - c[i]*v[i + 2])/b[i];
+ }
+ //----------------------------------------------------------------------
+
+ //Check if the internal voltages are in increasing order
+ is_found_valid_v = true;
+ for(int i = 1; i <= (int)eff_num_stacks; ++i)
+ {
+ //If the ith internal voltage is not in increasing order
+ //(i-1)th transistor is in triode region
+ //Remove the transistors in triode region as it does not exist
+ if(v[i] < v[i - 1])
+ {
+ is_found_valid_v = false;
+ eff_num_stacks--;
+ vs.erase(vs.begin() + i - 1);
+ ws.erase(ws.begin() + i - 1);
+ break;
+ }
+ }
+ } while(!is_found_valid_v);
+
+ //Calculate the leakage current of the bottom transistor (first not in triode region)
+ double vgs = vs[0] - v[0];
+ double vds = v[1] - v[0];
+ double leakage_current_factor = vgs/s1 + (vds - vdd_)/s2;
+ //TODO - Check if the leakage current calculate for other transistors is identical
+
+ return leakage_current_factor;
+ }
+ //-------------------------------------------------------------------------
+
+ //-------------------------------------------------------------------------
+ // Wire Related Functions
+ //-------------------------------------------------------------------------
+ bool TechModel::isWireLayerExist(const String& layer_name_) const
+ {
+ std::set<String>::const_iterator it;
+ it = m_available_wire_layers_->find(layer_name_);
+ return (it != m_available_wire_layers_->end());
+ }
+
+ const std::set<String>* TechModel::getAvailableWireLayers() const
+ {
+ return m_available_wire_layers_;
+ }
+
+ double TechModel::calculateWireCapacitance(const String& layer_name_, double width_, double spacing_, double length_) const
+ {
+ // Get technology parameter
+ double min_width = get("Wire->" + layer_name_ + "->MinWidth").toDouble();
+ double min_spacing = get("Wire->" + layer_name_ + "->MinSpacing").toDouble();
+ double metal_thickness = get("Wire->" + layer_name_ + "->MetalThickness").toDouble();
+ double dielec_thickness = get("Wire->" + layer_name_ + "->DielectricThickness").toDouble();
+ double dielec_const = get("Wire->" + layer_name_ + "->DielectricConstant").toDouble();
+
+ ASSERT(width_ >= min_width, "[Error] Wire width must be >= " + (String) min_width + "!");
+ ASSERT(spacing_ >= min_spacing, "[Error] Wire spacing must be >= " + (String) min_spacing + "!");
+ ASSERT(length_ >= 0, "[Error] Wire length must be >= 0!");
+
+ double A, B, C;
+ // Calculate ground capacitance
+ A = width_ / dielec_thickness;
+ B = 2.04*std::pow((spacing_ / (spacing_ + 0.54 * dielec_thickness)), 1.77);
+ C = std::pow((metal_thickness / (metal_thickness + 4.53 * dielec_thickness)), 0.07);
+ double unit_gnd_cap = dielec_const * 8.85e-12 * (A + B * C);
+
+ A = 1.14 * (metal_thickness / spacing_) * std::exp(-4.0 * spacing_ / (spacing_ + 8.01 * dielec_thickness));
+ B = 2.37 * std::pow((width_ / (width_ + 0.31 * spacing_)), 0.28);
+ C = std::pow((dielec_thickness / (dielec_thickness + 8.96 * spacing_)), 0.76) *
+ std::exp(-2.0 * spacing_ / (spacing_ + 6.0 * dielec_thickness));
+ double unit_coupling_cap = dielec_const * 8.85e-12 * (A + B * C);
+
+ double total_cap = 2 * (unit_gnd_cap + unit_coupling_cap) * length_;
+ return total_cap;
+ }
+
+ double TechModel::calculateWireResistance(const String& layer_name_, double width_, double length_) const
+ {
+ // Get technology parameter
+ double min_width = get("Wire->" + layer_name_ + "->MinWidth");
+ //double barrier_thickness = get("Wire->" + layer_name_ + "->BarrierThickness");
+ double resistivity = get("Wire->" + layer_name_ + "->Resistivity");
+ double metal_thickness = get("Wire->" + layer_name_ + "->MetalThickness");
+
+ ASSERT(width_ >= min_width, "[Error] Wire width must be >= " + (String) min_width + "!");
+ ASSERT(length_ >= 0, "[Error] Wire length must be >= 0!");
+
+ // Calculate Rho
+ // double rho = 2.202e-8 + (1.030e-15 / (width_ - 2.0 * barrier_thickness));
+
+ double unit_res = resistivity / (width_ * metal_thickness);
+ //double unit_res = rho / ((width_ - 2.0 * barrier_thickness) * (metal_thickness - barrier_thickness));
+
+ double total_res = unit_res * length_;
+ return total_res;
+ }
+ //-------------------------------------------------------------------------
+
+ TechModel::TechModel(const TechModel& tech_model_)
+ : Config(tech_model_), m_std_cell_lib_(tech_model_.m_std_cell_lib_)
+ {}
+} // namespace DSENT
+
diff --git a/ext/dsent/tech/TechModel.h b/ext/dsent/tech/TechModel.h
new file mode 100644
index 000000000..92e5a30ac
--- /dev/null
+++ b/ext/dsent/tech/TechModel.h
@@ -0,0 +1,71 @@
+#ifndef __DSENT_TECH_TECH_MODEL_H__
+#define __DSENT_TECH_TECH_MODEL_H__
+
+#include <vector>
+#include <set>
+
+#include "libutil/Config.h"
+#include "libutil/String.h"
+
+namespace DSENT
+{
+ class StdCellLib;
+
+ using std::set;
+ using std::vector;
+ using LibUtil::String;
+
+ class TechModel : public LibUtil::Config
+ {
+ public:
+ typedef std::set<String>::const_iterator ConstWireLayerIterator;
+
+ public:
+ TechModel();
+ virtual ~TechModel();
+
+ public:
+ // Set the pointer to a standard cell library
+ void setStdCellLib(const StdCellLib* std_cell_lib_);
+ // Get the pointer to the standard cell library
+ const StdCellLib* getStdCellLib() const;
+
+ // Return a cloned copy of this instance
+ virtual TechModel* clone() const;
+ // Override readFile function to include multiple technology files
+ virtual void readFile(const String& filename_);
+
+ // Transistor
+ // Returns the leakage current of NMOS transistors, given the transistor stakcing, transistor widths, and input combination
+ double calculateNmosLeakageCurrent(unsigned int num_stacks_, double uni_stacked_mos_width_, unsigned int input_vector_) const;
+ double calculateNmosLeakageCurrent(unsigned int num_stacks_, const vector<double>& stacked_mos_widths_, unsigned int input_vector_) const;
+ // Returns the leakage current of PMOS transistors, given the transistor stakcing, transistor widths, and input combination
+ double calculatePmosLeakageCurrent(unsigned int num_stacks_, double uni_stacked_mos_width_, unsigned int input_vector_) const;
+ double calculatePmosLeakageCurrent(unsigned int num_stacks_, const vector<double>& stacked_mos_widths_, unsigned int input_vector_) const;
+ // Returns the leakage current, given the transistor stakcing, transistor widths, input combination,
+ // and technology information (vdd, subthreshold swing, subthreshold dibl swing)
+ double calculateLeakageCurrentFactor(unsigned int num_stacks_, const vector<double>& stacked_mos_widths_, unsigned int input_vector_, double vdd_, double subthreshold_swing_, double dibl_swing_) const;
+
+ // Wire
+ // Check if the wire layer exist
+ bool isWireLayerExist(const String& layer_name_) const;
+ const std::set<String>* getAvailableWireLayers() const;
+ // Return wire capacitance for given wire layer, wire width, wire spacing, and wire length
+ double calculateWireCapacitance(const String& layer_name_, double width_, double spacing_, double length_) const;
+ // Return wire resistance for given wire layer, wire width, and wire length
+ double calculateWireResistance(const String& layer_name_, double width_, double length_) const;
+
+ private:
+ // Private copy constructor. Use clone to perform copy operation
+ TechModel(const TechModel& tech_model_);
+
+ private:
+ // A pointer to a standard cell library
+ const StdCellLib* m_std_cell_lib_;
+ // A set of available wire layers
+ std::set<String>* m_available_wire_layers_;
+ }; // class TechModel
+} // namespace DSENT
+
+#endif // __DSENT_TECH_TECH_MODEL_H__
+
diff --git a/ext/dsent/tech/tech_models/Bulk22LVT.model b/ext/dsent/tech/tech_models/Bulk22LVT.model
new file mode 100644
index 000000000..e2087a12d
--- /dev/null
+++ b/ext/dsent/tech/tech_models/Bulk22LVT.model
@@ -0,0 +1,179 @@
+# WARNING: Most commercial fabs will not be happy if you release their exact
+# process information! If you derive these numbers through SPICE models,
+# the process design kit, or any other confidential material, please round-off
+# the values and leave the process name unidentifiable by fab (i.e. call it
+# Bulk90LVT instead of TSMC90LVT) if you release parameters publicly. This
+# rule may not apply for open processes, but you may want to check.
+
+# All units are in SI, (volts, meters, kelvin, farads, ohms, amps, etc.)
+
+# This file contains the model for a bulk 22nm LVT process
+Name = Bulk22LVT
+
+# Supply voltage used in the circuit and for characterizations (V)
+Vdd = 0.8
+# Temperature (K)
+Temperature = 340
+
+# =============================================================================
+# Parameters for transistors
+# =============================================================================
+
+# Contacted gate pitch (m)
+Gate->PitchContacted = 0.120e-6
+
+# Min gate width (m)
+Gate->MinWidth = 0.100e-6
+
+# Gate cap per unit width (F/m)
+Gate->CapPerWidth = 0.900e-9
+# Source/Drain cap per unit width (F/m)
+Drain->CapPerWidth = 0.620e-9
+
+# Parameters characterization temperature (K)
+Nmos->CharacterizedTemperature = 300.0
+Pmos->CharacterizedTemperature = 300.0
+
+#------------------------------------------------------------------------------
+# I_Eff definition in Na, IEDM 2002
+# I_EFF = (I(VG = 0.5, VD = 1.0) + I(VG = 1.0, VD = 0.5))/2
+# R_EFF = VDD / I_EFF * 1 / (2 ln(2))
+# This is generally accurate for when input and output transition times
+# are similar, which is a reasonable case after timing optimization
+#------------------------------------------------------------------------------
+# Effective resistance (Ohm-m)
+Nmos->EffResWidth = 0.700e-3
+Pmos->EffResWidth = 0.930e-3
+
+#------------------------------------------------------------------------------
+# The ratio of extra effective resistance with each additional stacked
+# transistor
+# EffResStackRatio = (R_EFF_NAND2 - R_EFF_INV) / R_EFF_INV)
+# For example, inverter has an normalized effective drive resistance of 1.0.
+# A NAND2 (2-stack) will have an effective drive of 1.0 + 0.7, a NAND3 (3-stack)
+# will have an effective drive of 1.0 + 2 * 0.7. Use NORs for Pmos. This fit
+# works relatively well up to 4 stacks. This value will change depending on the
+# VDD used.
+#------------------------------------------------------------------------------
+# Effective resistance stack ratio
+Nmos->EffResStackRatio = 0.800
+Pmos->EffResStackRatio = 0.680
+
+#------------------------------------------------------------------------------
+# I_OFF defined as |I_DS| for |V_DS| = V_DD and |V_GS| = 0.0
+# Minimum off current is used in technologies where I_OFF stops scaling
+# with transistor width below some threshold
+#------------------------------------------------------------------------------
+# Off current per width (A/m)
+Nmos->OffCurrent = 100.0e-3
+Pmos->OffCurrent = 100.0e-3
+# Minimum off current (A)
+Nmos->MinOffCurrent = 60e-9
+Pmos->MinOffCurrent = 60e-9
+
+# Subthreshold swing (V/dec)
+Nmos->SubthresholdSwing = 0.100
+Pmos->SubthresholdSwing = 0.100
+# DIBL factor (V/V)
+Nmos->DIBL = 0.150
+Pmos->DIBL = 0.150
+# Subthreshold temperature swing (K/dec)
+Nmos->SubthresholdTempSwing = 100.0
+Pmos->SubthresholdTempSwing = 100.0
+#------------------------------------------------------------------------------
+
+# =============================================================================
+# Parameters for interconnect
+# =============================================================================
+
+Wire->AvailableLayers = [Metal1,Local,Intermediate,Semiglobal,Global]
+
+# Metal 1 Wire (used for std cell routing only)
+# Min width (m)
+Wire->Metal1->MinWidth = 32e-9
+# Min spacing (m)
+Wire->Metal1->MinSpacing = 32e-9
+# Resistivity (Ohm-m)
+Wire->Metal1->Resistivity = 5.00e-8
+# Metal thickness (m)
+Wire->Metal1->MetalThickness = 60.0e-9
+# Dielectric thickness (m)
+Wire->Metal1->DielectricThickness = 60.0e-9
+# Dielectric constant
+Wire->Metal1->DielectricConstant = 3.00
+
+# Local wire, 1.0X of the M1 pitch
+# Min width (m)
+Wire->Local->MinWidth = 32e-9
+# Min spacing (m)
+Wire->Local->MinSpacing = 32e-9
+# Resistivity (Ohm-m)
+Wire->Local->Resistivity = 5.00e-8
+# Metal thickness (m)
+Wire->Local->MetalThickness = 60.0e-9
+# Dielectric thickness (m)
+Wire->Local->DielectricThickness = 60.0e-9
+# Dielectric constant
+Wire->Local->DielectricConstant = 3.00
+
+# Intermediate wire, 2.0X the M1 pitch
+# Min width (m)
+Wire->Intermediate->MinWidth = 55e-9
+# Min spacing (m)
+Wire->Intermediate->MinSpacing = 55e-9
+# Resistivity (Ohm-m)
+Wire->Intermediate->Resistivity = 4.00e-8
+# Metal thickness (m)
+Wire->Intermediate->MetalThickness = 100.0e-9
+# Dielectric thickness (m)
+Wire->Intermediate->DielectricThickness = 100.0e-9
+# Dielectric constant
+Wire->Intermediate->DielectricConstant = 2.8
+
+# Semiglobal wire, 4.0X the M1 pitch
+# Min width (m)
+Wire->Semiglobal->MinWidth = 110e-9
+# Min spacing (m)
+Wire->Semiglobal->MinSpacing = 110e-9
+# Resistivity (Ohm-m)
+Wire->Semiglobal->Resistivity = 2.60e-8
+# Metal thickness (m)
+Wire->Semiglobal->MetalThickness = 200e-9
+# Dielectric thickness (m)
+Wire->Semiglobal->DielectricThickness = 170e-9
+# Dielectric constant
+Wire->Semiglobal->DielectricConstant = 2.80
+
+# Global wire, 6.0X the M1 pitch
+# Min width (m)
+Wire->Global->MinWidth = 160e-9
+# Min spacing (m)
+Wire->Global->MinSpacing = 160e-9
+# Resistivity (Ohm-m)
+Wire->Global->Resistivity = 2.30e-8
+# Metal thickness (m)
+Wire->Global->MetalThickness = 280e-9
+# Dielectric thickness (m)
+Wire->Global->DielectricThickness = 250e-9
+# Dielectric constant
+Wire->Global->DielectricConstant = 2.60
+
+# =============================================================================
+# Parameters for Standard Cells
+# =============================================================================
+
+# The height of the standard cell is usually a multiple of the vertical
+# M1 pitch (tracks). By definition, an X1 size cell has transistors
+# that fit exactly in the given cell height without folding, or leaving
+# any wasted vertical area
+
+# Reasonable values for the number of M1 tracks that we have seen are 8-14
+StdCell->Tracks = 11
+# Height overhead due to supply rails, well spacing, etc. Note that this will grow
+# if the height of the standard cell decreases!
+StdCell->HeightOverheadFactor = 1.400
+
+# Sets the available sizes of each standard cell. Keep in mind that
+# 1.0 is the biggest cell without any transistor folding
+StdCell->AvailableSizes = [1.0, 1.4, 2.0, 3.0, 4.0, 6.0, 8.0, 10.0, 12.0, 16.0]
+
diff --git a/ext/dsent/tech/tech_models/Bulk32LVT.model b/ext/dsent/tech/tech_models/Bulk32LVT.model
new file mode 100644
index 000000000..9a90bdaf9
--- /dev/null
+++ b/ext/dsent/tech/tech_models/Bulk32LVT.model
@@ -0,0 +1,168 @@
+# WARNING: Most commercial fabs will not be happy if you release their exact
+# process information! If you derive these numbers through SPICE models,
+# the process design kit, or any other confidential material, please round-off
+# the values and leave the process name unidentifiable by fab (i.e. call it
+# Bulk90LVT instead of TSMC90LVT) if you release parameters publicly. This
+# rule may not apply for open processes, but you may want to check.
+
+# All units are in SI, (volts, meters, kelvin, farads, ohms, amps, etc.)
+
+# This file contains the model for a bulk 32nm LVT process
+Name = Bulk32LVT
+
+# Supply voltage used in the circuit and for characterizations (V)
+Vdd = 0.9
+# Temperature (K)
+Temperature = 340
+
+# =============================================================================
+# Parameters for transistors
+# =============================================================================
+
+# Contacted gate pitch (m)
+Gate->PitchContacted = 0.160e-6
+
+# Min gate width (m)
+Gate->MinWidth = 0.120e-6
+
+# Gate cap per unit width (F/m)
+Gate->CapPerWidth = 0.950e-9
+# Source/Drain cap per unit width (F/m)
+Drain->CapPerWidth = 0.640e-9
+
+# Parameters characterization temperature (K)
+Nmos->CharacterizedTemperature = 300.0
+Pmos->CharacterizedTemperature = 300.0
+
+#------------------------------------------------------------------------------
+# I_Eff definition in Na, IEDM 2002
+# I_EFF = (I(VG = 0.5, VD = 1.0) + I(VG = 1.0, VD = 0.5))/2
+# R_EFF = VDD / I_EFF * 1 / (2 ln(2))
+# This is generally accurate for when input and output transition times
+# are similar, which is a reasonable case after timing optimization
+#------------------------------------------------------------------------------
+# Effective resistance (Ohm-m)
+Nmos->EffResWidth = 0.890e-3
+Pmos->EffResWidth = 1.270e-3
+
+#------------------------------------------------------------------------------
+# The ratio of extra effective resistance with each additional stacked
+# transistor
+# EffResStackRatio = (R_EFF_NAND2 - R_EFF_INV) / R_EFF_INV)
+# For example, inverter has an normalized effective drive resistance of 1.0.
+# A NAND2 (2-stack) will have an effective drive of 1.0 + 0.7, a NAND3 (3-stack)
+# will have an effective drive of 1.0 + 2 * 0.7. Use NORs for Pmos. This fit
+# works relatively well up to 4 stacks. This value will change depending on the
+# VDD used.
+#------------------------------------------------------------------------------
+# Effective resistance stack ratio
+Nmos->EffResStackRatio = 0.78
+Pmos->EffResStackRatio = 0.66
+
+#------------------------------------------------------------------------------
+# I_OFF defined as |I_DS| for |V_DS| = V_DD and |V_GS| = 0.0
+# Minimum off current is used as a second fit point, since I_OFF often
+# stops scaling with transistor width below some threshold
+#------------------------------------------------------------------------------
+# Off current per width (A/m)
+Nmos->OffCurrent = 100e-3
+Pmos->OffCurrent = 100e-3
+
+# Minimum off current (A)
+Nmos->MinOffCurrent = 100e-9
+Pmos->MinOffCurrent = 20e-9
+
+# Subthreshold swing (V/dec)
+Nmos->SubthresholdSwing = 0.100
+Pmos->SubthresholdSwing = 0.100
+
+# DIBL factor (V/V)
+Nmos->DIBL = 0.150
+Pmos->DIBL = 0.150
+
+# Subthreshold leakage temperature swing (K/dec)
+Nmos->SubthresholdTempSwing = 100
+Pmos->SubthresholdTempSwing = 100
+#------------------------------------------------------------------------------
+
+# =============================================================================
+# Parameters for interconnect
+# =============================================================================
+
+Wire->AvailableLayers = [Metal1,Local,Intermediate,Global]
+
+# Metal 1 Wire (used for std cell routing only)
+# Min width (m)
+Wire->Metal1->MinWidth = 55e-9
+# Min spacing (m)
+Wire->Metal1->MinSpacing = 55e-9
+# Resistivity (Ohm-m)
+Wire->Metal1->Resistivity = 4.00e-8
+# Metal thickness (m)
+Wire->Metal1->MetalThickness = 100.0e-9
+# Dielectric thickness (m)
+Wire->Metal1->DielectricThickness = 100.0e-9
+# Dielectric constant
+Wire->Metal1->DielectricConstant = 3.2
+
+# Local wire, 1.0X of the M1 pitch
+# Min width (m)
+Wire->Local->MinWidth = 55e-9
+# Min spacing (m)
+Wire->Local->MinSpacing = 55e-9
+# Resistivity (Ohm-m)
+Wire->Local->Resistivity = 4.00e-8
+# Metal thickness (m)
+Wire->Local->MetalThickness = 100.0e-9
+# Dielectric thickness (m)
+Wire->Local->DielectricThickness = 100.0e-9
+# Dielectric constant
+Wire->Local->DielectricConstant = 3.2
+
+# Intermediate wire, 2.0X the M1 pitch
+# Min width (m)
+Wire->Intermediate->MinWidth = 110e-9
+# Min spacing (m)
+Wire->Intermediate->MinSpacing = 110e-9
+# Resistivity (Ohm-m)
+Wire->Intermediate->Resistivity = 2.60e-8
+# Metal thickness (m)
+Wire->Intermediate->MetalThickness = 200e-9
+# Dielectric thickness (m)
+Wire->Intermediate->DielectricThickness = 170e-9
+# Dielectric constant
+Wire->Intermediate->DielectricConstant = 3.00
+
+# Global wire, 3.0X the M1 pitch
+# Min width (m)
+Wire->Global->MinWidth = 160e-9
+# Min spacing (m)
+Wire->Global->MinSpacing = 160e-9
+# Resistivity (Ohm-m)
+Wire->Global->Resistivity = 2.30e-8
+# Metal thickness (m)
+Wire->Global->MetalThickness = 280e-9
+# Dielectric thickness (m)
+Wire->Global->DielectricThickness = 250e-9
+# Dielectric constant
+Wire->Global->DielectricConstant = 2.80
+
+# =============================================================================
+# Parameters for Standard Cells
+# =============================================================================
+
+# The height of the standard cell is usually a multiple of the vertical
+# M1 pitch (tracks). By definition, an X1 size cell has transistors
+# that fit exactly in the given cell height without folding, or leaving
+# any wasted vertical area
+
+# Reasonable values for the number of M1 tracks that we have seen are 8-14
+StdCell->Tracks = 11
+# Height overhead due to supply rails, well spacing, etc. Note that this will grow
+# if the height of the standard cell decreases!
+StdCell->HeightOverheadFactor = 1.400
+
+# Sets the available sizes of each standard cell. Keep in mind that
+# 1.0 is the biggest cell without any transistor folding
+StdCell->AvailableSizes = [1.0, 1.4, 2.0, 3.0, 4.0, 6.0, 8.0, 10.0, 12.0, 16.0]
+
diff --git a/ext/dsent/tech/tech_models/Bulk45LVT.model b/ext/dsent/tech/tech_models/Bulk45LVT.model
new file mode 100644
index 000000000..d8015c522
--- /dev/null
+++ b/ext/dsent/tech/tech_models/Bulk45LVT.model
@@ -0,0 +1,168 @@
+# WARNING: Most commercial fabs will not be happy if you release their exact
+# process information! If you derive these numbers through SPICE models,
+# the process design kit, or any other confidential material, please round-off
+# the values and leave the process name unidentifiable by fab (i.e. call it
+# Bulk90LVT instead of TSMC90LVT) if you release parameters publicly. This
+# rule may not apply for open processes, but you may want to check.
+
+# All units are in SI, (volts, meters, kelvin, farads, ohms, amps, etc.)
+
+# This file contains the model for a bulk 45nm LVT process
+Name = Bulk45LVT
+
+# Supply voltage used in the circuit and for characterizations (V)
+Vdd = 1.0
+# Temperature (K)
+Temperature = 340
+
+# =============================================================================
+# Parameters for transistors
+# =============================================================================
+
+# Contacted gate pitch (m)
+Gate->PitchContacted = 0.200e-6
+
+# Min gate width (m)
+Gate->MinWidth = 0.160e-6
+
+# Gate cap per unit width (F/m)
+Gate->CapPerWidth = 1.000e-9
+# Source/Drain cap per unit width (F/m)
+Drain->CapPerWidth = 0.600e-9
+
+# Parameters characterization temperature (K)
+Nmos->CharacterizedTemperature = 300.0
+Pmos->CharacterizedTemperature = 300.0
+
+#------------------------------------------------------------------------------
+# I_Eff definition in Na, IEDM 2002
+# I_EFF = (I(VG = 0.5, VD = 1.0) + I(VG = 1.0, VD = 0.5))/2
+# R_EFF = VDD / I_EFF * 1 / (2 ln(2))
+# This is generally accurate for when input and output transition times
+# are similar, which is a reasonable case after timing optimization
+#------------------------------------------------------------------------------
+# Effective resistance (Ohm-m)
+Nmos->EffResWidth = 1.100e-3
+Pmos->EffResWidth = 1.500e-3
+
+#------------------------------------------------------------------------------
+# The ratio of extra effective resistance with each additional stacked
+# transistor
+# EffResStackRatio = (R_EFF_NAND2 - R_EFF_INV) / R_EFF_INV)
+# For example, inverter has an normalized effective drive resistance of 1.0.
+# A NAND2 (2-stack) will have an effective drive of 1.0 + 0.7, a NAND3 (3-stack)
+# will have an effective drive of 1.0 + 2 * 0.7. Use NORs for Pmos. This fit
+# works relatively well up to 4 stacks. This value will change depending on the
+# VDD used.
+#------------------------------------------------------------------------------
+# Effective resistance stack ratio
+Nmos->EffResStackRatio = 0.7
+Pmos->EffResStackRatio = 0.6
+
+#------------------------------------------------------------------------------
+# I_OFF defined as |I_DS| for |V_DS| = V_DD and |V_GS| = 0.0
+# Minimum off current is used as a second fit point, since I_OFF often
+# stops scaling with transistor width below some threshold
+#------------------------------------------------------------------------------
+# Off current per width (A/m)
+Nmos->OffCurrent = 100e-3
+Pmos->OffCurrent = 100e-3
+
+# Minimum off current (A)
+Nmos->MinOffCurrent = 100e-9
+Pmos->MinOffCurrent = 20e-9
+
+# Subthreshold swing (V/dec)
+Nmos->SubthresholdSwing = 0.100
+Pmos->SubthresholdSwing = 0.100
+
+# DIBL factor (V/V)
+Nmos->DIBL = 0.150
+Pmos->DIBL = 0.150
+
+# Subthreshold leakage temperature swing (K/dec)
+Nmos->SubthresholdTempSwing = 100
+Pmos->SubthresholdTempSwing = 100
+#------------------------------------------------------------------------------
+
+# =============================================================================
+# Parameters for interconnect
+# =============================================================================
+
+Wire->AvailableLayers = [Metal1,Local,Intermediate,Global]
+
+# Metal 1 Wire (used for std cell routing only)
+# Min width (m)
+Wire->Metal1->MinWidth = 80e-9
+# Min spacing (m)
+Wire->Metal1->MinSpacing = 80e-9
+# Resistivity (Ohm-m)
+Wire->Metal1->Resistivity = 3.00e-8
+# Metal thickness (m)
+Wire->Metal1->MetalThickness = 140.0e-9
+# Dielectric thickness (m)
+Wire->Metal1->DielectricThickness = 130.0e-9
+# Dielectric constant
+Wire->Metal1->DielectricConstant = 3.2
+
+# Local wire, 1.0X of the M1 pitch
+# Min width (m)
+Wire->Metal1->MinWidth = 80e-9
+# Min spacing (m)
+Wire->Metal1->MinSpacing = 80e-9
+# Resistivity (Ohm-m)
+Wire->Metal1->Resistivity = 3.00e-8
+# Metal thickness (m)
+Wire->Metal1->MetalThickness = 140.0e-9
+# Dielectric thickness (m)
+Wire->Metal1->DielectricThickness = 130.0e-9
+# Dielectric constant
+Wire->Metal1->DielectricConstant = 3.2
+
+# Intermediate wire, 1.4X the M1 pitch
+# Min width (m)
+Wire->Intermediate->MinWidth = 110e-9
+# Min spacing (m)
+Wire->Intermediate->MinSpacing = 110e-9
+# Resistivity (Ohm-m)
+Wire->Intermediate->Resistivity = 2.60e-8
+# Metal thickness (m)
+Wire->Intermediate->MetalThickness = 200e-9
+# Dielectric thickness (m)
+Wire->Intermediate->DielectricThickness = 170e-9
+# Dielectric constant
+Wire->Intermediate->DielectricConstant = 3.00
+
+# Global wire, 2.0X the M1 pitch
+# Min width (m)
+Wire->Global->MinWidth = 160e-9
+# Min spacing (m)
+Wire->Global->MinSpacing = 160e-9
+# Resistivity (Ohm-m)
+Wire->Global->Resistivity = 2.30e-8
+# Metal thickness (m)
+Wire->Global->MetalThickness = 280e-9
+# Dielectric thickness (m)
+Wire->Global->DielectricThickness = 250e-9
+# Dielectric constant
+Wire->Global->DielectricConstant = 2.80
+
+# =============================================================================
+# Parameters for Standard Cells
+# =============================================================================
+
+# The height of the standard cell is usually a multiple of the vertical
+# M1 pitch (tracks). By definition, an X1 size cell has transistors
+# that fit exactly in the given cell height without folding, or leaving
+# any wasted vertical area
+
+# Reasonable values for the number of M1 tracks that we have seen are 8-14
+StdCell->Tracks = 11
+# Height overhead due to supply rails, well spacing, etc. Note that this will grow
+# if the height of the standard cell decreases!
+StdCell->HeightOverheadFactor = 1.400
+
+# Sets the available sizes of each standard cell. Keep in mind that
+# 1.0 is the biggest cell without any transistor folding
+StdCell->AvailableSizes = [1.0, 1.4, 2.0, 3.0, 4.0, 6.0, 8.0, 10.0, 12.0, 16.0]
+
diff --git a/ext/dsent/tech/tech_models/Photonics.model b/ext/dsent/tech/tech_models/Photonics.model
new file mode 100644
index 000000000..335e1e832
--- /dev/null
+++ b/ext/dsent/tech/tech_models/Photonics.model
@@ -0,0 +1,89 @@
+# This file contains the model for photonic devices/circuits
+PhotonicsName = Photonics
+
+# ALL PARAMETERS IN SI UNITS!!! (J, W, m, F, dB, A)
+
+# -----------------------------------------------------------------------------
+# Waveguide
+# -----------------------------------------------------------------------------
+Waveguide->LossPerMeter = 100 # dB/m
+Waveguide->Pitch = 4e-6 # m
+Splitter->Loss = 1.00 # dB
+Coupler->Loss = 1.00 # dB
+
+# -----------------------------------------------------------------------------
+# Laser
+# -----------------------------------------------------------------------------
+
+# Continuous wave off-chip (always on) laser
+Laser->CW->Efficiency = 0.25 # P_Laser/P_Electrical
+Laser->CW->LaserDiodeLoss = 1.00 # Laser diode loss
+Laser->CW->Area = 0
+
+# Gated on-chip (data-dependent) laser
+Laser->GatedCW->Efficiency = 0.25 # P_Laser/P_Electrical
+Laser->GatedCW->LaserDiodeLoss = 1.00 # Laser diode loss
+Laser->GatedCW->Area = 200e-12
+
+# -----------------------------------------------------------------------------
+# Modulators
+# -----------------------------------------------------------------------------
+# Ring Modulator
+Modulator->Ring->SupplyBoostRatio = 1.2 # Boost the supply voltage above required reverse bias voltage by this ratio
+Modulator->Ring->ParasiticRes = 100 # ohm
+Modulator->Ring->ParasiticCap = 5e-15 # F
+Modulator->Ring->FCPDEffect = 3e-27 # Free carrier plasma dispersion effect, delta_n/delta_c (m^-3)
+Modulator->Ring->Tn = 0.01 # Transmisivity at the bottom of the notch
+Modulator->Ring->NA = 3e24 # m^3, p doping
+Modulator->Ring->ND = 1e24 # m^3, n doping
+Modulator->Ring->ni = 1e16 # m^3, intrinsic free carriers
+Modulator->Ring->JunctionRatio = 0.8 # Junction ratio to total optical length
+Modulator->Ring->Height = 500e-9 # Height of the junction (m)
+Modulator->Ring->Width = 500e-9 # Modulator width (m)
+Modulator->Ring->ConfinementFactor = 0.3 # Modulator confinement factor
+
+# -----------------------------------------------------------------------------
+# Ring Resonator
+# -----------------------------------------------------------------------------
+Ring->Area = 100e-12 # m2
+Ring->Lambda = 1300e-9 # Resonant wavelength range
+Ring->GroupIndex = 4 # Group index
+Ring->Radius = 3e-6 # Bend radius of the ring
+Ring->ConfinementFactor = 0.3 # Confinement factor
+Ring->ThroughLoss = 0.01 # [dB]
+Ring->DropLoss = 1.0 # [dB]
+Ring->MaxQualityFactor = 150e3 # Maximum quality factor
+Ring->HeatingEfficiency = 100000 # Ring heating efficiency [K/W]
+Ring->TuningEfficiency = 10e9 # Ring tuning efficiency [Hz/K]
+Ring->LocalVariationSigma = 40e9 # Ring resonance frequency local mismatch sigma [Hz]
+Ring->SystematicVariationSigma = 200e9 # Ring resonance frequency systematic mismatch sigma [Hz]
+Ring->TemperatureMax = 380 # Maximum temperature that the tuning mechanism must still be able to work at [K]
+Ring->TemperatureMin = 280 # Minimum temperature that the tuning mechanism must still be able to work at [K]
+Ring->MaxElectricallyTunableFreq = 50e9 # Maximum electrically tunable range when allowing for electrically assisted tuning [Hz]
+
+# -----------------------------------------------------------------------------
+# Photodetector
+# -----------------------------------------------------------------------------
+Photodetector->Responsivity = 1.1 #(A/W)
+Photodetector->Area = 10e-12 # m2
+Photodetector->Cap = 0 # F
+Photodetector->ParasiticCap = 5e-15 # F
+Photodetector->Loss = 1.00 # dB
+Photodetector->MinExtinctionRatio = 3 # dB
+Photodetector->AvalancheGain = 1 # avalanche gain
+
+# -----------------------------------------------------------------------------
+# Receivers
+# -----------------------------------------------------------------------------
+
+# Sense amplifier (common to all receivers)
+SenseAmp->BER = 1e-15 # Target bit error rate
+SenseAmp->CMRR = 5 # Common-mode rejection ratio
+SenseAmp->OffsetCompensationBits = 5 # Number of bits used for fine-tuning offset compensation
+SenseAmp->OffsetRatio = 0.04 # Offset mismatch (as a fraction of VDD)
+SenseAmp->SupplyNoiseRandRatio = 0.01 # Random supply noise (as a fraction VDD)
+SenseAmp->SupplyNoiseDetRatio = 0.05 # Deterministic supply noise (as a fraction VDD)
+SenseAmp->NoiseMargin = 0.02 # Extra noise margin
+SenseAmp->JitterRatio = 0.01 # Jitter (as a fraction of Tbit)
+
+Receiver->Int->IntegrationTimeRatio = 0.7 # Integration time (as a fraction of Tbit)
diff --git a/ext/dsent/tech/tech_models/TG11LVT.model b/ext/dsent/tech/tech_models/TG11LVT.model
new file mode 100644
index 000000000..292e40ab0
--- /dev/null
+++ b/ext/dsent/tech/tech_models/TG11LVT.model
@@ -0,0 +1,181 @@
+# WARNING: Most commercial fabs will not be happy if you release their exact
+# process information! If you derive these numbers through SPICE models,
+# the process design kit, or any other confidential material, please round-off
+# the values and leave the process name unidentifiable by fab (i.e. call it
+# Bulk90LVT instead of TSMC90LVT) if you release parameters publicly. This
+# rule may not apply for open processes, but you may want to check.
+
+# All units are in SI, (volts, meters, kelvin, farads, ohms, amps, etc.)
+
+# This file contains the model for a Tri-Gate (Multi-Gate) 11nm LVT process
+Name = TG11LVT
+
+# Supply voltage used in the circuit and for characterizations (V)
+Vdd = 0.6
+# Temperature (K)
+Temperature = 340
+
+# =============================================================================
+# Parameters for transistors
+# =============================================================================
+
+# Contacted gate pitch (m)
+Gate->PitchContacted = 0.080e-6
+
+# Min gate width (m)
+Gate->MinWidth = 0.080e-6
+
+# Gate cap per unit width (F/m)
+Gate->CapPerWidth = 0.61e-9
+# Source/Drain cap per unit width (F/m)
+Drain->CapPerWidth = 0.56e-9
+
+# Parameters characterization temperature (K)
+Nmos->CharacterizedTemperature = 300.0
+Pmos->CharacterizedTemperature = 300.0
+
+#------------------------------------------------------------------------------
+# I_Eff definition in Na, IEDM 2002
+# I_EFF = (I(VG = 0.5, VD = 1.0) + I(VG = 1.0, VD = 0.5))/2
+# R_EFF = VDD / I_EFF * 1 / (2 ln(2))
+# This is generally more accurate for when the delay is input transition time
+# limited
+#------------------------------------------------------------------------------
+# Effective resistance (Ohm-m)
+Nmos->EffResWidth = 1.16e-3
+Pmos->EffResWidth = 1.28e-3
+
+#------------------------------------------------------------------------------
+# The ratio of extra effective resistance with each additional stacked
+# transistor
+# EffResStackRatio = (R_EFF_NAND2 - R_EFF_INV) / R_EFF_INV)
+# For example, inverter has an normalized effective drive resistance of 1.0.
+# A NAND2 (2-stack) will have an effective drive of 1.0 + 0.7, a NAND3 (3-stack)
+# will have an effective drive of 1.0 + 2 * 0.7. Use NORs for Pmos. This fit
+# works relatively well up to 4 stacks. This value will change depending on the
+# VDD used.
+#------------------------------------------------------------------------------
+# Effective resistance stack ratio
+Nmos->EffResStackRatio = 0.89
+Pmos->EffResStackRatio = 0.86
+
+#------------------------------------------------------------------------------
+# I_OFF defined as |I_DS| for |V_DS| = V_DD and |V_GS| = 0.0
+# Minimum off current is used in technologies where I_OFF stops scaling
+# with transistor width below some threshold
+#------------------------------------------------------------------------------
+# Off current per width (A/m)
+Nmos->OffCurrent = 100.0e-3
+Pmos->OffCurrent = 100.0e-3
+# Minimum off current (A)
+Nmos->MinOffCurrent = 40e-9
+Pmos->MinOffCurrent = 4e-9
+
+# Subthreshold swing (V/dec)
+Nmos->SubthresholdSwing = 0.080
+Pmos->SubthresholdSwing = 0.080
+# DIBL factor (V/V)
+Nmos->DIBL = 0.125
+Pmos->DIBL = 0.125
+# Subthreshold temperature swing (K/dec)
+Nmos->SubthresholdTempSwing = 100.0
+Pmos->SubthresholdTempSwing = 100.0
+#------------------------------------------------------------------------------
+
+# =============================================================================
+# Parameters for interconnect
+# =============================================================================
+
+Wire->AvailableLayers = [Metal1,Local,Intermediate,Semiglobal,Global]
+
+# Metal 1 Wire (used for std cell routing only)
+# Min width (m)
+Wire->Metal1->MinWidth = 20e-9
+# Min spacing (m)
+Wire->Metal1->MinSpacing = 20e-9
+# Resistivity (Ohm-m)
+Wire->Metal1->Resistivity = 6.8e-8
+# Metal thickness (m)
+Wire->Metal1->MetalThickness = 35.0e-9
+# Dielectric thickness (m)
+Wire->Metal1->DielectricThickness = 35.0e-9
+# Dielectric constant
+Wire->Metal1->DielectricConstant = 3.00
+
+# Local wire, 1.0X of the M1 pitch
+# Min width (m)
+Wire->Local->MinWidth = 20e-9
+# Min spacing (m)
+Wire->Local->MinSpacing = 20e-9
+# Resistivity (Ohm-m)
+Wire->Local->Resistivity = 6.8e-8
+# Metal thickness (m)
+Wire->Local->MetalThickness = 35.0e-9
+# Dielectric thickness (m)
+Wire->Local->DielectricThickness = 35.0e-9
+# Dielectric constant
+Wire->Local->DielectricConstant = 3.00
+
+# Intermediate wire, 2.0X the M1 pitch
+# Min width (m)
+Wire->Intermediate->MinWidth = 40e-9
+# Min spacing (m)
+Wire->Intermediate->MinSpacing = 40e-9
+# Resistivity (Ohm-m)
+Wire->Intermediate->Resistivity = 4.50e-8
+# Metal thickness (m)
+Wire->Intermediate->MetalThickness = 70.0e-9
+# Dielectric thickness (m)
+Wire->Intermediate->DielectricThickness = 70.0e-9
+# Dielectric constant
+Wire->Intermediate->DielectricConstant = 2.80
+
+# Semiglobal wire, 4.0X the M1 pitch
+# Min width (m)
+Wire->Semiglobal->MinWidth = 80e-9
+# Min spacing (m)
+Wire->Semiglobal->MinSpacing = 80e-9
+# Resistivity (Ohm-m)
+Wire->Semiglobal->Resistivity = 2.80e-8
+# Metal thickness (m)
+Wire->Semiglobal->MetalThickness = 150.0e-9
+# Dielectric thickness (m)
+Wire->Semiglobal->DielectricThickness = 150.0e-9
+# Dielectric constant
+Wire->Semiglobal->DielectricConstant = 2.60
+
+# Global wire, 8.0X the M1 pitch
+# Min width (m)
+Wire->Global->MinWidth = 160e-9
+# Min spacing (m)
+Wire->Global->MinSpacing = 160e-9
+# Resistivity (Ohm-m)
+Wire->Global->Resistivity = 2.30e-8
+# Metal thickness (m)
+Wire->Global->MetalThickness = 280e-9
+# Dielectric thickness (m)
+Wire->Global->DielectricThickness = 250e-9
+# Dielectric constant
+Wire->Global->DielectricConstant = 2.60
+
+# =============================================================================
+# Parameters for Standard Cells
+# =============================================================================
+
+# The height of the standard cell is usually a multiple of the vertical
+# M1 pitch (tracks). By definition, an X1 size cell has transistors
+# that fit exactly in the given cell height without folding, or leaving
+# any wasted vertical area
+
+# Reasonable values for the number of M1 tracks that we have seen are 8-14
+StdCell->Tracks = 11
+# Height overhead due to supply rails, well spacing, etc. Note that this will grow
+# if the height of the standard cell decreases!
+StdCell->HeightOverheadFactor = 1.400
+
+# Sets the available sizes of each standard cell. Keep in mind that
+# 1.0 is the biggest cell without any transistor folding
+StdCell->AvailableSizes = [1.0, 1.4, 2.0, 3.0, 4.0, 6.0, 8.0, 10.0, 12.0, 16.0]
+
+
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 04:48:55 +0000