diff options
Diffstat (limited to 'ext/gdb-xml')
| -rw-r--r-- | ext/gdb-xml/aarch64-core.xml | 67 | ||||
| -rw-r--r-- | ext/gdb-xml/aarch64-fpu.xml | 86 | ||||
| -rw-r--r-- | ext/gdb-xml/aarch64.xml | 14 | ||||
| -rw-r--r-- | ext/gdb-xml/arm/arm-core.xml | 31 | ||||
| -rw-r--r-- | ext/gdb-xml/arm/arm-vfpv3.xml | 44 | ||||
| -rw-r--r-- | ext/gdb-xml/arm/arm-with-neon.xml | 14 |
6 files changed, 256 insertions, 0 deletions
diff --git a/ext/gdb-xml/aarch64-core.xml b/ext/gdb-xml/aarch64-core.xml new file mode 100644 index 000000000..eb6364eb0 --- /dev/null +++ b/ext/gdb-xml/aarch64-core.xml @@ -0,0 +1,67 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2009-2018 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.aarch64.core"> + <reg name="x0" bitsize="64"/> + <reg name="x1" bitsize="64"/> + <reg name="x2" bitsize="64"/> + <reg name="x3" bitsize="64"/> + <reg name="x4" bitsize="64"/> + <reg name="x5" bitsize="64"/> + <reg name="x6" bitsize="64"/> + <reg name="x7" bitsize="64"/> + <reg name="x8" bitsize="64"/> + <reg name="x9" bitsize="64"/> + <reg name="x10" bitsize="64"/> + <reg name="x11" bitsize="64"/> + <reg name="x12" bitsize="64"/> + <reg name="x13" bitsize="64"/> + <reg name="x14" bitsize="64"/> + <reg name="x15" bitsize="64"/> + <reg name="x16" bitsize="64"/> + <reg name="x17" bitsize="64"/> + <reg name="x18" bitsize="64"/> + <reg name="x19" bitsize="64"/> + <reg name="x20" bitsize="64"/> + <reg name="x21" bitsize="64"/> + <reg name="x22" bitsize="64"/> + <reg name="x23" bitsize="64"/> + <reg name="x24" bitsize="64"/> + <reg name="x25" bitsize="64"/> + <reg name="x26" bitsize="64"/> + <reg name="x27" bitsize="64"/> + <reg name="x28" bitsize="64"/> + <reg name="x29" bitsize="64"/> + <reg name="x30" bitsize="64"/> + <reg name="sp" bitsize="64" type="data_ptr"/> + + <reg name="pc" bitsize="64" type="code_ptr"/> + + <flags id="cpsr_flags" size="4"> + <field name="SP" start="0" end="0"/> + <field name="" start="1" end="1"/> + <field name="EL" start="2" end="3"/> + <field name="nRW" start="4" end="4"/> + <field name="" start="5" end="5"/> + <field name="F" start="6" end="6"/> + <field name="I" start="7" end="7"/> + <field name="A" start="8" end="8"/> + <field name="D" start="9" end="9"/> + + <field name="IL" start="20" end="20"/> + <field name="SS" start="21" end="21"/> + + <field name="V" start="28" end="28"/> + <field name="C" start="29" end="29"/> + <field name="Z" start="30" end="30"/> + <field name="N" start="31" end="31"/> + </flags> + <reg name="cpsr" bitsize="32" type="cpsr_flags"/> + +</feature> diff --git a/ext/gdb-xml/aarch64-fpu.xml b/ext/gdb-xml/aarch64-fpu.xml new file mode 100644 index 000000000..399099a8e --- /dev/null +++ b/ext/gdb-xml/aarch64-fpu.xml @@ -0,0 +1,86 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2009-2018 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.aarch64.fpu"> + <vector id="v2d" type="ieee_double" count="2"/> + <vector id="v2u" type="uint64" count="2"/> + <vector id="v2i" type="int64" count="2"/> + <vector id="v4f" type="ieee_single" count="4"/> + <vector id="v4u" type="uint32" count="4"/> + <vector id="v4i" type="int32" count="4"/> + <vector id="v8u" type="uint16" count="8"/> + <vector id="v8i" type="int16" count="8"/> + <vector id="v16u" type="uint8" count="16"/> + <vector id="v16i" type="int8" count="16"/> + <vector id="v1u" type="uint128" count="1"/> + <vector id="v1i" type="int128" count="1"/> + <union id="vnd"> + <field name="f" type="v2d"/> + <field name="u" type="v2u"/> + <field name="s" type="v2i"/> + </union> + <union id="vns"> + <field name="f" type="v4f"/> + <field name="u" type="v4u"/> + <field name="s" type="v4i"/> + </union> + <union id="vnh"> + <field name="u" type="v8u"/> + <field name="s" type="v8i"/> + </union> + <union id="vnb"> + <field name="u" type="v16u"/> + <field name="s" type="v16i"/> + </union> + <union id="vnq"> + <field name="u" type="v1u"/> + <field name="s" type="v1i"/> + </union> + <union id="aarch64v"> + <field name="d" type="vnd"/> + <field name="s" type="vns"/> + <field name="h" type="vnh"/> + <field name="b" type="vnb"/> + <field name="q" type="vnq"/> + </union> + <reg name="v0" bitsize="128" type="aarch64v" regnum="34"/> + <reg name="v1" bitsize="128" type="aarch64v" /> + <reg name="v2" bitsize="128" type="aarch64v" /> + <reg name="v3" bitsize="128" type="aarch64v" /> + <reg name="v4" bitsize="128" type="aarch64v" /> + <reg name="v5" bitsize="128" type="aarch64v" /> + <reg name="v6" bitsize="128" type="aarch64v" /> + <reg name="v7" bitsize="128" type="aarch64v" /> + <reg name="v8" bitsize="128" type="aarch64v" /> + <reg name="v9" bitsize="128" type="aarch64v" /> + <reg name="v10" bitsize="128" type="aarch64v"/> + <reg name="v11" bitsize="128" type="aarch64v"/> + <reg name="v12" bitsize="128" type="aarch64v"/> + <reg name="v13" bitsize="128" type="aarch64v"/> + <reg name="v14" bitsize="128" type="aarch64v"/> + <reg name="v15" bitsize="128" type="aarch64v"/> + <reg name="v16" bitsize="128" type="aarch64v"/> + <reg name="v17" bitsize="128" type="aarch64v"/> + <reg name="v18" bitsize="128" type="aarch64v"/> + <reg name="v19" bitsize="128" type="aarch64v"/> + <reg name="v20" bitsize="128" type="aarch64v"/> + <reg name="v21" bitsize="128" type="aarch64v"/> + <reg name="v22" bitsize="128" type="aarch64v"/> + <reg name="v23" bitsize="128" type="aarch64v"/> + <reg name="v24" bitsize="128" type="aarch64v"/> + <reg name="v25" bitsize="128" type="aarch64v"/> + <reg name="v26" bitsize="128" type="aarch64v"/> + <reg name="v27" bitsize="128" type="aarch64v"/> + <reg name="v28" bitsize="128" type="aarch64v"/> + <reg name="v29" bitsize="128" type="aarch64v"/> + <reg name="v30" bitsize="128" type="aarch64v"/> + <reg name="v31" bitsize="128" type="aarch64v"/> + <reg name="fpsr" bitsize="32"/> + <reg name="fpcr" bitsize="32"/> +</feature> diff --git a/ext/gdb-xml/aarch64.xml b/ext/gdb-xml/aarch64.xml new file mode 100644 index 000000000..2b87cd326 --- /dev/null +++ b/ext/gdb-xml/aarch64.xml @@ -0,0 +1,14 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2009-2018 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE target SYSTEM "gdb-target.dtd"> +<target> + <architecture>aarch64</architecture> + <xi:include href="aarch64-core.xml"/> + <xi:include href="aarch64-fpu.xml"/> +</target> diff --git a/ext/gdb-xml/arm/arm-core.xml b/ext/gdb-xml/arm/arm-core.xml new file mode 100644 index 000000000..dc9b3cf0f --- /dev/null +++ b/ext/gdb-xml/arm/arm-core.xml @@ -0,0 +1,31 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2007-2018 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.arm.core"> + <reg name="r0" bitsize="32" type="uint32"/> + <reg name="r1" bitsize="32" type="uint32"/> + <reg name="r2" bitsize="32" type="uint32"/> + <reg name="r3" bitsize="32" type="uint32"/> + <reg name="r4" bitsize="32" type="uint32"/> + <reg name="r5" bitsize="32" type="uint32"/> + <reg name="r6" bitsize="32" type="uint32"/> + <reg name="r7" bitsize="32" type="uint32"/> + <reg name="r8" bitsize="32" type="uint32"/> + <reg name="r9" bitsize="32" type="uint32"/> + <reg name="r10" bitsize="32" type="uint32"/> + <reg name="r11" bitsize="32" type="uint32"/> + <reg name="r12" bitsize="32" type="uint32"/> + <reg name="sp" bitsize="32" type="data_ptr"/> + <reg name="lr" bitsize="32"/> + <reg name="pc" bitsize="32" type="code_ptr"/> + + <!-- The CPSR is register 25, rather than register 16, because + the FPA registers historically were placed between the PC + and the CPSR in the "g" packet. --> + <reg name="cpsr" bitsize="32" regnum="25"/> +</feature> diff --git a/ext/gdb-xml/arm/arm-vfpv3.xml b/ext/gdb-xml/arm/arm-vfpv3.xml new file mode 100644 index 000000000..37e136f6d --- /dev/null +++ b/ext/gdb-xml/arm/arm-vfpv3.xml @@ -0,0 +1,44 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2009-2018 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE feature SYSTEM "gdb-target.dtd"> +<feature name="org.gnu.gdb.arm.vfp"> + <reg name="d0" bitsize="64" type="ieee_double"/> + <reg name="d1" bitsize="64" type="ieee_double"/> + <reg name="d2" bitsize="64" type="ieee_double"/> + <reg name="d3" bitsize="64" type="ieee_double"/> + <reg name="d4" bitsize="64" type="ieee_double"/> + <reg name="d5" bitsize="64" type="ieee_double"/> + <reg name="d6" bitsize="64" type="ieee_double"/> + <reg name="d7" bitsize="64" type="ieee_double"/> + <reg name="d8" bitsize="64" type="ieee_double"/> + <reg name="d9" bitsize="64" type="ieee_double"/> + <reg name="d10" bitsize="64" type="ieee_double"/> + <reg name="d11" bitsize="64" type="ieee_double"/> + <reg name="d12" bitsize="64" type="ieee_double"/> + <reg name="d13" bitsize="64" type="ieee_double"/> + <reg name="d14" bitsize="64" type="ieee_double"/> + <reg name="d15" bitsize="64" type="ieee_double"/> + <reg name="d16" bitsize="64" type="ieee_double"/> + <reg name="d17" bitsize="64" type="ieee_double"/> + <reg name="d18" bitsize="64" type="ieee_double"/> + <reg name="d19" bitsize="64" type="ieee_double"/> + <reg name="d20" bitsize="64" type="ieee_double"/> + <reg name="d21" bitsize="64" type="ieee_double"/> + <reg name="d22" bitsize="64" type="ieee_double"/> + <reg name="d23" bitsize="64" type="ieee_double"/> + <reg name="d24" bitsize="64" type="ieee_double"/> + <reg name="d25" bitsize="64" type="ieee_double"/> + <reg name="d26" bitsize="64" type="ieee_double"/> + <reg name="d27" bitsize="64" type="ieee_double"/> + <reg name="d28" bitsize="64" type="ieee_double"/> + <reg name="d29" bitsize="64" type="ieee_double"/> + <reg name="d30" bitsize="64" type="ieee_double"/> + <reg name="d31" bitsize="64" type="ieee_double"/> + + <reg name="fpscr" bitsize="32" type="int" group="float"/> +</feature> diff --git a/ext/gdb-xml/arm/arm-with-neon.xml b/ext/gdb-xml/arm/arm-with-neon.xml new file mode 100644 index 000000000..6818caccd --- /dev/null +++ b/ext/gdb-xml/arm/arm-with-neon.xml @@ -0,0 +1,14 @@ +<?xml version="1.0"?> +<!-- Copyright (C) 2009-2018 Free Software Foundation, Inc. + + Copying and distribution of this file, with or without modification, + are permitted in any medium without royalty provided the copyright + notice and this notice are preserved. --> + +<!DOCTYPE target SYSTEM "gdb-target.dtd"> +<target> + <architecture>arm</architecture> + <xi:include href="arm-core.xml"/> + <xi:include href="arm-vfpv3.xml"/> + <feature name="org.gnu.gdb.arm.neon"/> +</target> |