summaryrefslogtreecommitdiff
path: root/ext/mcpat/cacti/cacti_interface.cc
diff options
context:
space:
mode:
Diffstat (limited to 'ext/mcpat/cacti/cacti_interface.cc')
-rw-r--r--ext/mcpat/cacti/cacti_interface.cc183
1 files changed, 82 insertions, 101 deletions
diff --git a/ext/mcpat/cacti/cacti_interface.cc b/ext/mcpat/cacti/cacti_interface.cc
index b6d0d13de..b397db897 100644
--- a/ext/mcpat/cacti/cacti_interface.cc
+++ b/ext/mcpat/cacti/cacti_interface.cc
@@ -2,6 +2,7 @@
* McPAT/CACTI
* SOFTWARE LICENSE AGREEMENT
* Copyright 2012 Hewlett-Packard Development Company, L.P.
+ * Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
* All Rights Reserved
*
* Redistribution and use in source and binary forms, with or without
@@ -25,7 +26,7 @@
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
@@ -47,127 +48,107 @@
using namespace std;
-bool mem_array::lt(const mem_array * m1, const mem_array * m2)
-{
- if (m1->Nspd < m2->Nspd) return true;
- else if (m1->Nspd > m2->Nspd) return false;
- else if (m1->Ndwl < m2->Ndwl) return true;
- else if (m1->Ndwl > m2->Ndwl) return false;
- else if (m1->Ndbl < m2->Ndbl) return true;
- else if (m1->Ndbl > m2->Ndbl) return false;
- else if (m1->deg_bl_muxing < m2->deg_bl_muxing) return true;
- else if (m1->deg_bl_muxing > m2->deg_bl_muxing) return false;
- else if (m1->Ndsam_lev_1 < m2->Ndsam_lev_1) return true;
- else if (m1->Ndsam_lev_1 > m2->Ndsam_lev_1) return false;
- else if (m1->Ndsam_lev_2 < m2->Ndsam_lev_2) return true;
- else return false;
+bool mem_array::lt(const mem_array * m1, const mem_array * m2) {
+ if (m1->Nspd < m2->Nspd) return true;
+ else if (m1->Nspd > m2->Nspd) return false;
+ else if (m1->Ndwl < m2->Ndwl) return true;
+ else if (m1->Ndwl > m2->Ndwl) return false;
+ else if (m1->Ndbl < m2->Ndbl) return true;
+ else if (m1->Ndbl > m2->Ndbl) return false;
+ else if (m1->deg_bl_muxing < m2->deg_bl_muxing) return true;
+ else if (m1->deg_bl_muxing > m2->deg_bl_muxing) return false;
+ else if (m1->Ndsam_lev_1 < m2->Ndsam_lev_1) return true;
+ else if (m1->Ndsam_lev_1 > m2->Ndsam_lev_1) return false;
+ else if (m1->Ndsam_lev_2 < m2->Ndsam_lev_2) return true;
+ else return false;
}
-void uca_org_t::find_delay()
-{
- mem_array * data_arr = data_array2;
- mem_array * tag_arr = tag_array2;
-
- // check whether it is a regular cache or scratch ram
- if (g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc)
- {
- access_time = data_arr->access_time;
- }
- // Both tag and data lookup happen in parallel
- // and the entire set is sent over the data array h-tree without
- // waiting for the way-select signal --TODO add the corresponding
- // power overhead Nav
- else if (g_ip->fast_access == true)
- {
- access_time = MAX(tag_arr->access_time, data_arr->access_time);
- }
- // Tag is accessed first. On a hit, way-select signal along with the
- // address is sent to read/write the appropriate block in the data
- // array
- else if (g_ip->is_seq_acc == true)
- {
- access_time = tag_arr->access_time + data_arr->access_time;
- }
- // Normal access: tag array access and data array access happen in parallel.
- // But, the data array will wait for the way-select and transfer only the
- // appropriate block over the h-tree.
- else
- {
- access_time = MAX(tag_arr->access_time + data_arr->delay_senseamp_mux_decoder,
- data_arr->delay_before_subarray_output_driver) +
- data_arr->delay_from_subarray_output_driver_to_output;
- }
+void uca_org_t::find_delay() {
+ mem_array * data_arr = data_array2;
+ mem_array * tag_arr = tag_array2;
+
+ // check whether it is a regular cache or scratch ram
+ if (g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc) {
+ access_time = data_arr->access_time;
+ }
+ // Both tag and data lookup happen in parallel
+ // and the entire set is sent over the data array h-tree without
+ // waiting for the way-select signal --TODO add the corresponding
+ // power overhead Nav
+ else if (g_ip->fast_access == true) {
+ access_time = MAX(tag_arr->access_time, data_arr->access_time);
+ }
+ // Tag is accessed first. On a hit, way-select signal along with the
+ // address is sent to read/write the appropriate block in the data
+ // array
+ else if (g_ip->is_seq_acc == true) {
+ access_time = tag_arr->access_time + data_arr->access_time;
+ }
+ // Normal access: tag array access and data array access happen in parallel.
+ // But, the data array will wait for the way-select and transfer only the
+ // appropriate block over the h-tree.
+ else {
+ access_time = MAX(tag_arr->access_time + data_arr->delay_senseamp_mux_decoder,
+ data_arr->delay_before_subarray_output_driver) +
+ data_arr->delay_from_subarray_output_driver_to_output;
+ }
}
-void uca_org_t::find_energy()
-{
- if (!(g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc))//(g_ip->is_cache)
- power = data_array2->power + tag_array2->power;
- else
- power = data_array2->power;
+void uca_org_t::find_energy() {
+ if (!(g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc))
+ power = data_array2->power + tag_array2->power;
+ else
+ power = data_array2->power;
}
-void uca_org_t::find_area()
-{
- if (g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc)//(g_ip->is_cache == false)
- {
- cache_ht = data_array2->height;
- cache_len = data_array2->width;
- }
- else
- {
- cache_ht = MAX(tag_array2->height, data_array2->height);
- cache_len = tag_array2->width + data_array2->width;
- }
- area = cache_ht * cache_len;
+void uca_org_t::find_area() {
+ if (g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc) {
+ cache_ht = data_array2->height;
+ cache_len = data_array2->width;
+ } else {
+ cache_ht = MAX(tag_array2->height, data_array2->height);
+ cache_len = tag_array2->width + data_array2->width;
+ }
+ area = cache_ht * cache_len;
}
-void uca_org_t::adjust_area()
-{
- double area_adjust;
- if (g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc)
- {
- if (data_array2->area_efficiency/100.0<0.2)
- {
- //area_adjust = sqrt(area/(area*(data_array2->area_efficiency/100.0)/0.2));
- area_adjust = sqrt(0.2/(data_array2->area_efficiency/100.0));
- cache_ht = cache_ht/area_adjust;
- cache_len = cache_len/area_adjust;
+void uca_org_t::adjust_area() {
+ double area_adjust;
+ if (g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc) {
+ if (data_array2->area_efficiency / 100.0 < 0.2) {
+ //area_adjust = sqrt(area/(area*(data_array2->area_efficiency/100.0)/0.2));
+ area_adjust = sqrt(0.2 / (data_array2->area_efficiency / 100.0));
+ cache_ht = cache_ht / area_adjust;
+ cache_len = cache_len / area_adjust;
+ }
}
- }
- area = cache_ht * cache_len;
+ area = cache_ht * cache_len;
}
-void uca_org_t::find_cyc()
-{
- if ((g_ip->pure_ram|| g_ip->pure_cam || g_ip->fully_assoc))//(g_ip->is_cache == false)
- {
- cycle_time = data_array2->cycle_time;
- }
- else
- {
- cycle_time = MAX(tag_array2->cycle_time,
- data_array2->cycle_time);
- }
+void uca_org_t::find_cyc() {
+ if ((g_ip->pure_ram || g_ip->pure_cam || g_ip->fully_assoc)) {
+ cycle_time = data_array2->cycle_time;
+ } else {
+ cycle_time = MAX(tag_array2->cycle_time,
+ data_array2->cycle_time);
+ }
}
uca_org_t :: uca_org_t()
-:tag_array2(0),
- data_array2(0)
-{
+ : tag_array2(0),
+ data_array2(0) {
}
-void uca_org_t :: cleanup()
-{
- if (data_array2!=0)
- delete data_array2;
- if (tag_array2!=0)
- delete tag_array2;
+void uca_org_t :: cleanup() {
+ if (data_array2 != 0)
+ delete data_array2;
+ if (tag_array2 != 0)
+ delete tag_array2;
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-26 22:24:45 +0000