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-rw-r--r--ext/mcpat/interconnect.h86
1 files changed, 46 insertions, 40 deletions
diff --git a/ext/mcpat/interconnect.h b/ext/mcpat/interconnect.h
index 4cf42dafd..2ae39c5a2 100644
--- a/ext/mcpat/interconnect.h
+++ b/ext/mcpat/interconnect.h
@@ -2,6 +2,7 @@
* McPAT
* SOFTWARE LICENSE AGREEMENT
* Copyright 2012 Hewlett-Packard Development Company, L.P.
+ * Copyright (c) 2010-2013 Advanced Micro Devices, Inc.
* All Rights Reserved
*
* Redistribution and use in source and binary forms, with or without
@@ -25,7 +26,7 @@
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.”
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
@@ -42,46 +43,31 @@
#include "subarray.h"
#include "wire.h"
-// leakge power includes entire htree in a bank (when uca_tree == false)
-// leakge power includes only part to one bank when uca_tree == true
+class InterconnectParameters {
+public:
+ double active_ports;
+};
-class interconnect : public Component
-{
- public:
- interconnect(
- string name_,
- enum Device_ty device_ty_,
- double base_w, double base_h, int data_w, double len,
- const InputParameter *configure_interface, int start_wiring_level_,
- bool pipelinable_ = false,
- double route_over_perc_ =0.5,
- bool opt_local_=true,
- enum Core_type core_ty_=Inorder,
- enum Wire_type wire_model=Global,
- double width_s=1.0, double space_s=1.0,
- TechnologyParameter::DeviceType *dt = &(g_tp.peri_global)
- );
+class InterconnectStatistics {
+public:
+ double duty_cycle;
+ double accesses;
+};
- ~interconnect() {};
+class Interconnect : public McPATComponent {
+public:
+ static double width_scaling_threshold;
- void compute();
- string name;
- enum Device_ty device_ty;
+ enum Device_ty device_ty;
double in_rise_time, out_rise_time;
- InputParameter l_ip;
- uca_org_t local_result;
+ InputParameter l_ip;
+ uca_org_t local_result;
Area no_device_under_wire_area;
- void set_in_rise_time(double rt)
- {
- in_rise_time = rt;
- }
-
- void leakage_feedback(double temperature);
double max_unpipelined_link_delay;
powerDef power_bit;
double wire_bw;
- double init_wire_bw; // bus width at root
+ double init_wire_bw;
double base_width;
double base_height;
int data_width;
@@ -92,19 +78,39 @@ class interconnect : public Component
double min_w_nmos;
double min_w_pmos;
double latency, throughput;
- bool latency_overflow;
- bool throughput_overflow;
- double interconnect_latency;
- double interconnect_throughput;
+ bool latency_overflow;
+ bool throughput_overflow;
+ double interconnect_latency;
+ double interconnect_throughput;
bool opt_local;
enum Core_type core_ty;
bool pipelinable;
double route_over_perc;
- int num_pipe_stages;
-
- private:
- TechnologyParameter::DeviceType *deviceType;
+ int num_pipe_stages;
+ TechnologyParameter::DeviceType* deviceType;
+ InterconnectParameters int_params;
+ InterconnectStatistics int_stats;
+ Interconnect(XMLNode* _xml_data, string name_,
+ enum Device_ty device_ty_, double base_w,
+ double base_h, int data_w, double len,
+ const InputParameter *configure_interface,
+ int start_wiring_level_,
+ double _clockRate = 0.0f,
+ bool pipelinable_ = false, double route_over_perc_ = 0.5,
+ bool opt_local_ = true, enum Core_type core_ty_ = Inorder,
+ enum Wire_type wire_model = Global, double width_s = 1.0,
+ double space_s = 1.0,
+ TechnologyParameter::DeviceType *dt = &(g_tp.peri_global));
+private:
+ void calcWireData();
+public:
+ void computeArea();
+ void computeEnergy();
+ void set_params_stats(double active_ports,
+ double duty_cycle, double accesses);
+ void leakage_feedback(double temperature);
+ ~Interconnect() {};
};
#endif