diff options
Diffstat (limited to 'ext/mcpat/regression/test-1/power_region0.xml')
| -rw-r--r-- | ext/mcpat/regression/test-1/power_region0.xml | 811 |
1 files changed, 811 insertions, 0 deletions
diff --git a/ext/mcpat/regression/test-1/power_region0.xml b/ext/mcpat/regression/test-1/power_region0.xml new file mode 100644 index 000000000..390c71150 --- /dev/null +++ b/ext/mcpat/regression/test-1/power_region0.xml @@ -0,0 +1,811 @@ +<?xml version="1.0" ?> +<component id="root" name="root"> + <component id="system" name="system" type="System"> + <param name="core_tech_node" value="40"/> + <param name="target_core_clockrate" value="3000"/> + <param name="temperature" value="360"/> + <param name="interconnect_projection_type" value="0"/> + <param name="device_type" value="0"/> + <param name="machine_bits" value="64"/> + <param name="virtual_address_width" value="64"/> + <param name="physical_address_width" value="52"/> + <param name="virtual_memory_page_size" value="4096"/> + <param name="wire_is_mat_type" value="2"/> + <param name="wire_os_mat_type" value="2"/> + <param name="delay_wt" value="100"/> + <param name="area_wt" value="0"/> + <param name="dynamic_power_wt" value="100"/> + <param name="leakage_power_wt" value="0"/> + <param name="cycle_time_wt" value="0"/> + <param name="delay_dev" value="10000"/> + <param name="area_dev" value="10000"/> + <param name="dynamic_power_dev" value="10000"/> + <param name="leakage_power_dev" value="10000"/> + <param name="cycle_time_dev" value="10000"/> + <param name="ed" value="2"/> + <param name="burst_len" value="1"/> + <param name="int_prefetch_w" value="1"/> + <param name="page_sz_bits" value="0"/> + <param name="rpters_in_htree" value="1"/> + <param name="ver_htree_wires_over_array" value="0"/> + <param name="nuca" value="0"/> + <param name="nuca_bank_count" value="0"/> + <param name="force_cache_config" value="0"/> + <param name="wt" value="0"/> + <param name="force_wiretype" value="0"/> + <param name="print_detail" value="1"/> + <param name="add_ecc_b_" value="1"/> + <stat name="total_cycles" value="1856694"/> + <component id="system.core0" name="core0" type="Core"> + <param name="opt_local" value="0"/> + <param name="clock_rate" value="2000"/> + <param name="instruction_length" value="32"/> + <param name="opcode_width" value="6"/> + <param name="machine_type" value="1"/> + <param name="number_hardware_threads" value="1"/> + <param name="fetch_width" value="1"/> + <param name="number_instruction_fetch_ports" value="1"/> + <param name="decode_width" value="1"/> + <param name="issue_width" value="1"/> + <param name="peak_issue_width" value="1"/> + <param name="commit_width" value="1"/> + <param name="fp_issue_width" value="1"/> + <param name="prediction_width" value="1"/> + <param name="int_pipelines" value="1"/> + <param name="fp_pipelines" value="1"/> + <param name="int_pipeline_depth" value="7"/> + <param name="fp_pipeline_depth" value="10"/> + <param name="ALU_per_core" value="1"/> + <param name="FPU_per_core" value="1"/> + <param name="MUL_per_core" value="1"/> + <param name="instruction_buffer_size" value="16"/> + <param name="instruction_window_scheme" value="0"/> + <param name="instruction_window_size" value="0"/> + <param name="fp_instruction_window_size" value="0"/> + <param name="ROB_size" value="0"/> + <param name="archi_Regs_IRF_size" value="32"/> + <param name="archi_Regs_FRF_size" value="32"/> + <param name="phy_Regs_IRF_size" value="32"/> + <param name="phy_Regs_FRF_size" value="32"/> + <param name="rename_scheme" value="0"/> + <param name="register_window_size" value="0"/> + <param name="store_buffer_size" value="8"/> + <param name="load_buffer_size" value="0"/> + <param name="memory_ports" value="1"/> + <param name="RAS_size" value="32"/> + <param name="execu_wire_mat_type" value="2"/> + <param name="execu_bypass_base_width" value="1"/> + <param name="execu_bypass_base_height" value="1"/> + <param name="execu_bypass_start_wiring_level"value="3"/> + <param name="execu_bypass_route_over_perc" value="1"/> + <param name="globalCheckpoint" value="32"/> + <param name="perThreadState" value="8"/> + <param name="ROB_assoc" value="1"/> + <param name="ROB_nbanks" value="1"/> + <param name="ROB_tag_width" value="0"/> + <param name="scheduler_assoc" value="0"/> + <param name="scheduler_nbanks" value="1"/> + <param name="register_window_assoc" value="1"/> + <param name="register_window_nbanks" value="1"/> + <param name="register_window_tag_width" value="0"/> + <param name="register_window_rw_ports" value="1"/> + <param name="phy_Regs_IRF_assoc" value="1"/> + <param name="phy_Regs_IRF_nbanks" value="1"/> + <param name="phy_Regs_IRF_tag_width" value="0"/> + <param name="phy_Regs_IRF_rd_ports" value="1"/> + <param name="phy_Regs_IRF_wr_ports" value="1"/> + <param name="phy_Regs_FRF_assoc" value="1"/> + <param name="phy_Regs_FRF_nbanks" value="1"/> + <param name="phy_Regs_FRF_tag_width" value="0"/> + <param name="phy_Regs_FRF_rd_ports" value="1"/> + <param name="phy_Regs_FRF_wr_ports" value="1"/> + <param name="front_rat_nbanks" value="1"/> + <param name="front_rat_rw_ports" value="1"/> + <param name="retire_rat_nbanks" value="1"/> + <param name="retire_rat_rw_ports" value="0"/> + <param name="freelist_nbanks" value="1"/> + <param name="freelist_rw_ports" value="1"/> + <param name="load_buffer_assoc" value="0"/> + <param name="load_buffer_nbanks" value="1"/> + <param name="store_buffer_assoc" value="0"/> + <param name="store_buffer_nbanks" value="1"/> + <param name="instruction_buffer_assoc" value="1"/> + <param name="instruction_buffer_nbanks" value="1"/> + <param name="instruction_buffer_tag_width" value="0"/> + <stat name="total_instructions" value="332405"/> + <stat name="int_instructions" value="330557"/> + <stat name="fp_instructions" value="1649"/> + <stat name="branch_instructions" value="8263"/> + <stat name="branch_mispredictions" value="53"/> + <stat name="load_instructions" value="45636"/> + <stat name="store_instructions" value="44771"/> + <stat name="committed_instructions" value="332405"/> + <stat name="committed_int_instructions" value="330557"/> + <stat name="committed_fp_instructions" value="1649"/> + <stat name="total_cycles" value="9496951709"/> + <stat name="idle_cycles" value="0"/> + <stat name="busy_cycles" value="9496951709"/> + <stat name="ROB_reads" value="332405"/> + <stat name="ROB_writes" value="332405"/> + <stat name="rename_reads" value="960725"/> + <stat name="rename_writes" value="317221"/> + <stat name="fp_rename_reads" value="2772"/> + <stat name="fp_rename_writes" value="1288"/> + <stat name="inst_window_reads" value="330557"/> + <stat name="inst_window_writes" value="330557"/> + <stat name="inst_window_wakeup_accesses" value="330557"/> + <stat name="fp_inst_window_reads" value="1649"/> + <stat name="fp_inst_window_writes" value="1649"/> + <stat name="fp_inst_window_wakeup_accesses" value="1649"/> + <stat name="int_regfile_reads" value="960725"/> + <stat name="float_regfile_reads" value="2772"/> + <stat name="int_regfile_writes" value="317221"/> + <stat name="float_regfile_writes" value="1288"/> + <stat name="function_calls" value="5"/> + <stat name="context_switches" value="1"/> + <stat name="ialu_accesses" value="330157"/> + <stat name="fpu_accesses" value="1649"/> + <stat name="mul_accesses" value="200"/> + <stat name="cdb_alu_accesses" value="330157"/> + <stat name="cdb_mul_accesses" value="200"/> + <stat name="cdb_fpu_accesses" value="1649"/> + <stat name="IFU_duty_cycle" value="1"/> + <stat name="LSU_duty_cycle" value="1"/> + <stat name="MemManU_I_duty_cycle" value="1"/> + <stat name="MemManU_D_duty_cycle" value="1"/> + <stat name="ALU_duty_cycle" value="1"/> + <stat name="MUL_duty_cycle" value="1"/> + <stat name="FPU_duty_cycle" value="1"/> + <stat name="ALU_cdb_duty_cycle" value="1"/> + <stat name="MUL_cdb_duty_cycle" value="1"/> + <stat name="FPU_cdb_duty_cycle" value="1"/> + <component id="system.core0.bpred" name="bpred" type="BranchPredictor"> + <param name="assoc" value="1"/> + <param name="nbanks" value="1"/> + <param name="local_l1_predictor_size" value="10"/> + <param name="local_l2_predictor_size" value="3"/> + <param name="local_predictor_entries" value="1024"/> + <param name="global_predictor_entries" value="4096"/> + <param name="global_predictor_bits" value="2"/> + <param name="chooser_predictor_entries" value="4096"/> + <param name="chooser_predictor_bits" value="2"/> + </component> + <component id="system.core0.itlb" name="itlb" type="InstructionTLB"> + <param name="number_entries" value="64"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="assoc" value="0"/> + <param name="nbanks" value="1"/> + <stat name="total_accesses" value="8263"/> + <stat name="total_misses" value="5"/> + <stat name="conflicts" value="1"/> + </component> + <component id="system.core0.dtlb" name="dtlb" type="DataTLB"> + <param name="number_entries" value="64"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="assoc" value="0"/> + <param name="nbanks" value="1"/> + <stat name="read_accesses" value="108476"/> + <stat name="write_accesses" value="78"/> + <stat name="read_misses" value="7"/> + <stat name="write_misses" value="0"/> + <stat name="conflicts" value="7"/> + </component> + <component id="system.core0.btargetbuf" name="btargetbuf" type="BranchTargetBuffer"> + <param name="size" value="8192"/> + <param name="block_size" value="4"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="1"/> + <param name="throughput" value="3"/> + <param name="rw_ports" value="1"/> + <stat name="read_accesses" value="43"/> + <stat name="write_accesses" value="943"/> + </component> + </component> + <component id="system.core1" name="core1" type="Core"> + <param name="opt_local" value="0"/> + <param name="clock_rate" value="2000"/> + <param name="instruction_length" value="32"/> + <param name="opcode_width" value="6"/> + <param name="machine_type" value="1"/> + <param name="number_hardware_threads" value="1"/> + <param name="fetch_width" value="1"/> + <param name="number_instruction_fetch_ports" value="1"/> + <param name="decode_width" value="1"/> + <param name="issue_width" value="1"/> + <param name="peak_issue_width" value="1"/> + <param name="commit_width" value="1"/> + <param name="fp_issue_width" value="1"/> + <param name="prediction_width" value="1"/> + <param name="int_pipelines" value="1"/> + <param name="fp_pipelines" value="1"/> + <param name="int_pipeline_depth" value="7"/> + <param name="fp_pipeline_depth" value="10"/> + <param name="ALU_per_core" value="1"/> + <param name="FPU_per_core" value="1"/> + <param name="MUL_per_core" value="1"/> + <param name="instruction_buffer_size" value="16"/> + <param name="instruction_window_scheme" value="0"/> + <param name="instruction_window_size" value="0"/> + <param name="fp_instruction_window_size" value="0"/> + <param name="ROB_size" value="0"/> + <param name="archi_Regs_IRF_size" value="32"/> + <param name="archi_Regs_FRF_size" value="32"/> + <param name="phy_Regs_IRF_size" value="32"/> + <param name="phy_Regs_FRF_size" value="32"/> + <param name="rename_scheme" value="0"/> + <param name="register_window_size" value="0"/> + <param name="store_buffer_size" value="8"/> + <param name="load_buffer_size" value="0"/> + <param name="memory_ports" value="1"/> + <param name="RAS_size" value="32"/> + <param name="execu_wire_mat_type" value="2"/> + <param name="execu_bypass_base_width" value="1"/> + <param name="execu_bypass_base_height" value="1"/> + <param name="execu_bypass_start_wiring_level"value="3"/> + <param name="execu_bypass_route_over_perc" value="1"/> + <param name="globalCheckpoint" value="32"/> + <param name="perThreadState" value="8"/> + <param name="ROB_assoc" value="1"/> + <param name="ROB_nbanks" value="1"/> + <param name="ROB_tag_width" value="0"/> + <param name="scheduler_assoc" value="0"/> + <param name="scheduler_nbanks" value="1"/> + <param name="register_window_assoc" value="1"/> + <param name="register_window_nbanks" value="1"/> + <param name="register_window_tag_width" value="0"/> + <param name="register_window_rw_ports" value="1"/> + <param name="phy_Regs_IRF_assoc" value="1"/> + <param name="phy_Regs_IRF_nbanks" value="1"/> + <param name="phy_Regs_IRF_tag_width" value="0"/> + <param name="phy_Regs_IRF_rd_ports" value="1"/> + <param name="phy_Regs_IRF_wr_ports" value="1"/> + <param name="phy_Regs_FRF_assoc" value="1"/> + <param name="phy_Regs_FRF_nbanks" value="1"/> + <param name="phy_Regs_FRF_tag_width" value="0"/> + <param name="phy_Regs_FRF_rd_ports" value="1"/> + <param name="phy_Regs_FRF_wr_ports" value="1"/> + <param name="front_rat_nbanks" value="1"/> + <param name="front_rat_rw_ports" value="1"/> + <param name="retire_rat_nbanks" value="1"/> + <param name="retire_rat_rw_ports" value="0"/> + <param name="freelist_nbanks" value="1"/> + <param name="freelist_rw_ports" value="1"/> + <param name="load_buffer_assoc" value="0"/> + <param name="load_buffer_nbanks" value="1"/> + <param name="store_buffer_assoc" value="0"/> + <param name="store_buffer_nbanks" value="1"/> + <param name="instruction_buffer_assoc" value="1"/> + <param name="instruction_buffer_nbanks" value="1"/> + <param name="instruction_buffer_tag_width" value="0"/> + <stat name="total_instructions" value="4358"/> + <stat name="int_instructions" value="4336"/> + <stat name="fp_instructions" value="22"/> + <stat name="branch_instructions" value="1358"/> + <stat name="branch_mispredictions" value="14"/> + <stat name="load_instructions" value="715"/> + <stat name="store_instructions" value="406"/> + <stat name="committed_instructions" value="4358"/> + <stat name="committed_int_instructions" value="4336"/> + <stat name="committed_fp_instructions" value="22"/> + <stat name="total_cycles" value="9496737874"/> + <stat name="ROB_reads" value="4358"/> + <stat name="ROB_writes" value="4358"/> + <stat name="rename_reads" value="12614"/> + <stat name="rename_writes" value="4404"/> + <stat name="fp_rename_reads" value="22"/> + <stat name="fp_rename_writes" value="22"/> + <stat name="inst_window_reads" value="4336"/> + <stat name="inst_window_writes" value="4336"/> + <stat name="inst_window_wakeup_accesses" value="4336"/> + <stat name="fp_inst_window_reads" value="22"/> + <stat name="fp_inst_window_writes" value="22"/> + <stat name="fp_inst_window_wakeup_accesses" value="22"/> + <stat name="int_regfile_reads" value="12614"/> + <stat name="float_regfile_reads" value="44"/> + <stat name="int_regfile_writes" value="4404"/> + <stat name="float_regfile_writes" value="22"/> + <stat name="function_calls" value="3"/> + <stat name="context_switches" value="1"/> + <stat name="ialu_accesses" value="4236"/> + <stat name="fpu_accesses" value="22"/> + <stat name="mul_accesses" value="100"/> + <stat name="cdb_alu_accesses" value="4236"/> + <stat name="cdb_mul_accesses" value="100"/> + <stat name="cdb_fpu_accesses" value="22"/> + <stat name="IFU_duty_cycle" value="1"/> + <stat name="LSU_duty_cycle" value="1"/> + <stat name="MemManU_I_duty_cycle" value="1"/> + <stat name="MemManU_D_duty_cycle" value="1"/> + <stat name="ALU_duty_cycle" value="1"/> + <stat name="MUL_duty_cycle" value="1"/> + <stat name="FPU_duty_cycle" value="1"/> + <stat name="ALU_cdb_duty_cycle" value="1"/> + <stat name="MUL_cdb_duty_cycle" value="1"/> + <stat name="FPU_cdb_duty_cycle" value="1"/> + <component id="system.core1.bpred" name="bpred" type="BranchPredictor"> + <param name="assoc" value="1"/> + <param name="nbanks" value="1"/> + <param name="local_l1_predictor_size" value="10"/> + <param name="local_l2_predictor_size" value="3"/> + <param name="local_predictor_entries" value="1024"/> + <param name="global_predictor_entries" value="4096"/> + <param name="global_predictor_bits" value="2"/> + <param name="chooser_predictor_entries" value="4096"/> + <param name="chooser_predictor_bits" value="2"/> + </component> + <component id="system.core1.itlb" name="itlb" type="InstructionTLB"> + <param name="number_entries" value="64"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="assoc" value="0"/> + <param name="nbanks" value="1"/> + <stat name="total_accesses" value="253291"/> + <stat name="total_misses" value="6"/> + <stat name="conflicts" value="5"/> + </component> + <component id="system.core1.dtlb" name="dtlb" type="DataTLB"> + <param name="number_entries" value="64"/> + <param name="latency" value="8"/> + <param name="throughput" value="3"/> + <param name="assoc" value="0"/> + <param name="nbanks" value="1"/> + <stat name="read_accesses" value="91498"/> + <stat name="write_accesses" value="29"/> + <stat name="read_misses" value="3"/> + <stat name="write_misses" value="0"/> + <stat name="conflicts" value="3"/> + </component> + <component id="system.core1.btargetbuf" name="btargetbuf" type="BranchTargetBuffer"> + <param name="size" value="8192"/> + <param name="block_size" value="4"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="1"/> + <param name="throughput" value="3"/> + <param name="rw_ports" value="1"/> + <stat name="read_accesses" value="43"/> + <stat name="write_accesses" value="943"/> + </component> + </component> + <component id="system.mc" name="mc" type="MemoryController"> + <param name="mc_clock" value="800"/> + <param name="tech_type" value="2"/> + <param name="mc_type" value="0"/> + <param name="num_mcs" value="1"/> + <param name="type" value="0"/> + <param name="LVDS" value="1"/> + <param name="withPHY" value="1"/> + <param name="llc_line_length" value="64"/> + <param name="memory_channels_per_mc" value="2"/> + <param name="req_window_size_per_channel" value="128"/> + <param name="IO_buffer_size_per_channel" value="128"/> + <param name="databus_width" value="128"/> + <param name="addressbus_width" value="51"/> + <param name="opcode_width" value="16"/> + <param name="peak_transfer_rate" value="6400"/> + <param name="number_ranks" value="2"/> + <param name="reorder_buffer_assoc" value="0"/> + <param name="reorder_buffer_nbanks" value="1"/> + <param name="read_buffer_assoc" value="1"/> + <param name="read_buffer_nbanks" value="1"/> + <param name="read_buffer_tag_width" value="0"/> + <param name="write_buffer_assoc" value="1"/> + <param name="write_buffer_nbanks" value="1"/> + <param name="write_buffer_tag_width" value="0"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <stat name="memory_reads" value="274"/> + <stat name="memory_writes" value="86"/> + <stat name="duty_cycle" value="0.5"/> + </component> + <component id="system.l1_cntrl0" name="l1_cntrl0" type="CacheController"> + <component id="system.l1_cntrl0.L1DcacheMemory" name="L1DcacheMemory" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="2"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="device_type" value="0"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="47291"/> + <stat name="num_data_array_writes" value="51619"/> + <stat name="num_tag_array_reads" value="91498"/> + <stat name="num_tag_array_writes" value="17078"/> + <stat name="read_misses" value="156"/> + <stat name="write_misses" value="92"/> + <stat name="conflicts" value="148"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.l1_cntrl0.L1IcacheMemory" name="L1IcacheMemory" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="2"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="device_type" value="0"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="253831"/> + <stat name="num_data_array_writes" value="3497"/> + <stat name="num_tag_array_reads" value="253291"/> + <stat name="num_tag_array_writes" value="10845"/> + <stat name="read_misses" value="456"/> + <stat name="write_misses" value="92"/> + <stat name="conflicts" value="448"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.l1_cntrl0.L2cacheMemory" name="L2cacheMemory" type="CacheUnit"> + <param name="level" value="2"/> + <param name="size" value="2097152"/> + <param name="block_size" value="64"/> + <param name="assoc" value="16"/> + <param name="num_banks" value="1"/> + <param name="latency" value="10"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="device_type" value="0"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="1"/> + <param name="miss_buff_access_mode" value="0"/> + <param name="fetch_buff_access_mode" value="0"/> + <param name="prefetch_buff_access_mode" value="0"/> + <param name="writeback_buff_access_mode"value="0"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="274"/> + <stat name="num_data_array_writes" value="8086"/> + <stat name="num_tag_array_reads" value="3959"/> + <stat name="num_tag_array_writes" value="12046"/> + <stat name="read_misses" value="56"/> + <stat name="write_misses" value="32"/> + <stat name="conflicts" value="88"/> + <stat name="duty_cycle" value="1"/> + </component> + </component> + <component id="system.l1_cntrl1" name="l1_cntrl1" type="CacheController"> + <component id="system.l1_cntrl1.L1DcacheMemory" name="L1DcacheMemory" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="2"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="device_type" value="0"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="631"/> + <stat name="num_data_array_writes" value="527"/> + <stat name="num_tag_array_reads" value="6356"/> + <stat name="num_tag_array_writes" value="297"/> + <stat name="read_misses" value="36"/> + <stat name="write_misses" value="12"/> + <stat name="conflicts" value="48"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.l1_cntrl1.L1IcacheMemory" name="L1IcacheMemory" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="2"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="device_type" value="0"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="2879"/> + <stat name="num_data_array_writes" value="182"/> + <stat name="num_tag_array_reads" value="8263"/> + <stat name="num_tag_array_writes" value="551"/> + <stat name="read_misses" value="156"/> + <stat name="write_misses" value="92"/> + <stat name="conflicts" value="148"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.l1_cntrl1.L2cacheMemory" name="L2cacheMemory" type="CacheUnit"> + <param name="level" value="2"/> + <param name="size" value="2097152"/> + <param name="block_size" value="64"/> + <param name="assoc" value="16"/> + <param name="num_banks" value="1"/> + <param name="latency" value="10"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="device_type" value="0"/> + <param name="clockrate" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="1"/> + <param name="miss_buff_access_mode" value="0"/> + <param name="fetch_buff_access_mode" value="0"/> + <param name="prefetch_buff_access_mode" value="0"/> + <param name="writeback_buff_access_mode"value="0"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="3"/> + <stat name="num_data_array_writes" value="10"/> + <stat name="num_tag_array_reads" value="5210"/> + <stat name="num_tag_array_writes" value="13"/> + <stat name="read_misses" value="462"/> + <stat name="write_misses" value="0"/> + <stat name="conflicts" value="462"/> + <stat name="duty_cycle" value="1"/> + </component> + </component> + </component> +</component> |