diff options
Diffstat (limited to 'ext/mcpat/regression/test-2/power_region0.xml')
| -rw-r--r-- | ext/mcpat/regression/test-2/power_region0.xml | 242 |
1 files changed, 242 insertions, 0 deletions
diff --git a/ext/mcpat/regression/test-2/power_region0.xml b/ext/mcpat/regression/test-2/power_region0.xml new file mode 100644 index 000000000..2c8521afb --- /dev/null +++ b/ext/mcpat/regression/test-2/power_region0.xml @@ -0,0 +1,242 @@ +<?xml version="1.0" ?> +<component id="root" name="root"> + <component id="system" name="system" type="System"> + <param name="core_tech_node" value="40"/> + <param name="target_core_clockrate" value="1400"/> + <param name="temperature" value="360"/> + <param name="interconnect_projection_type" value="0"/> + <param name="device_type" value="0"/> + <param name="machine_bits" value="64"/> + <param name="virtual_address_width" value="64"/> + <param name="physical_address_width" value="52"/> + <param name="virtual_memory_page_size" value="4096"/> + <param name="wire_is_mat_type" value="2"/> + <param name="wire_os_mat_type" value="2"/> + <param name="delay_wt" value="100"/> + <param name="area_wt" value="0"/> + <param name="dynamic_power_wt" value="100"/> + <param name="leakage_power_wt" value="0"/> + <param name="cycle_time_wt" value="0"/> + <param name="delay_dev" value="10000"/> + <param name="area_dev" value="10000"/> + <param name="dynamic_power_dev" value="10000"/> + <param name="leakage_power_dev" value="10000"/> + <param name="cycle_time_dev" value="10000"/> + <param name="ed" value="2"/> + <param name="burst_len" value="1"/> + <param name="int_prefetch_w" value="1"/> + <param name="page_sz_bits" value="0"/> + <param name="rpters_in_htree" value="1"/> + <param name="ver_htree_wires_over_array" value="0"/> + <param name="nuca" value="0"/> + <param name="nuca_bank_count" value="0"/> + <param name="force_cache_config" value="0"/> + <param name="wt" value="0"/> + <param name="force_wiretype" value="0"/> + <param name="print_detail" value="1"/> + <param name="add_ecc_b_" value="1"/> + <stat name="total_cycles" value="566948"/> + <component id="system.l1_cntrl0" name="l1_cntrl0" type="CacheController"> + <component id="system.l1_cntrl0.L1DcacheMemory" name="L1DcacheMemory" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="2"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="clockrate" value="2000"/> + <param name="device_type" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="47291"/> + <stat name="num_data_array_writes" value="51619"/> + <stat name="num_tag_array_reads" value="91498"/> + <stat name="num_tag_array_writes" value="17078"/> + <stat name="read_misses" value="174"/> + <stat name="write_misses" value="12046"/> + <stat name="conflicts" value="12120"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.l1_cntrl0.L1IcacheMemory" name="L1IcacheMemory" type="CacheUnit"> + <param name="level" value="1"/> + <param name="size" value="32768"/> + <param name="block_size" value="64"/> + <param name="assoc" value="2"/> + <param name="num_banks" value="1"/> + <param name="latency" value="2"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="clockrate" value="2000"/> + <param name="device_type" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="0"/> + <param name="miss_buff_access_mode" value="2"/> + <param name="fetch_buff_access_mode" value="2"/> + <param name="prefetch_buff_access_mode" value="2"/> + <param name="writeback_buff_access_mode"value="2"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="253831"/> + <stat name="num_data_array_writes" value="3497"/> + <stat name="num_tag_array_reads" value="253291"/> + <stat name="num_tag_array_writes" value="10845"/> + <stat name="read_misses" value="100"/> + <stat name="conflicts" value="99"/> + <stat name="duty_cycle" value="1"/> + </component> + <component id="system.l1_cntrl0.L2cacheMemory" name="L2cacheMemory" type="CacheUnit"> + <param name="level" value="2"/> + <param name="size" value="2097152"/> + <param name="block_size" value="64"/> + <param name="assoc" value="16"/> + <param name="num_banks" value="1"/> + <param name="latency" value="10"/> + <param name="throughput" value="1"/> + <param name="miss_buffer_size" value="2"/> + <param name="fetch_buffer_size" value="2"/> + <param name="prefetch_buffer_size" value="2"/> + <param name="writeback_buffer_size" value="2"/> + <param name="clockrate" value="2000"/> + <param name="device_type" value="0"/> + <param name="tech_type" value="0"/> + <param name="Directory_type" value="2"/> + <param name="core_type" value="1"/> + <param name="wire_mat_type" value="2"/> + <param name="wire_type" value="0"/> + <param name="miss_buffer_assoc" value="0"/> + <param name="fetch_buffer_assoc" value="0"/> + <param name="prefetch_buffer_assoc" value="0"/> + <param name="writeback_buffer_assoc" value="0"/> + <param name="miss_buffer_banks" value="1"/> + <param name="fetch_buffer_banks" value="1"/> + <param name="prefetch_buffer_banks" value="1"/> + <param name="writeback_buffer_banks" value="1"/> + <param name="cache_access_mode" value="1"/> + <param name="miss_buff_access_mode" value="0"/> + <param name="fetch_buff_access_mode" value="0"/> + <param name="prefetch_buff_access_mode" value="0"/> + <param name="writeback_buff_access_mode"value="0"/> + <param name="cache_rw_ports" value="1"/> + <param name="cache_rd_ports" value="0"/> + <param name="cache_wr_ports" value="0"/> + <param name="cache_se_rd_ports" value="0"/> + <param name="cache_search_ports" value="0"/> + <param name="miss_buff_rw_ports" value="1"/> + <param name="miss_buff_rd_ports" value="0"/> + <param name="miss_buff_wr_ports" value="0"/> + <param name="miss_buff_se_rd_ports" value="0"/> + <param name="miss_buff_search_ports" value="1"/> + <param name="fetch_buff_rw_ports" value="1"/> + <param name="fetch_buff_rd_ports" value="0"/> + <param name="fetch_buff_wr_ports" value="0"/> + <param name="fetch_buff_se_rd_ports" value="0"/> + <param name="fetch_buff_search_ports" value="1"/> + <param name="pf_buff_rw_ports" value="1"/> + <param name="pf_buff_rd_ports" value="0"/> + <param name="pf_buff_wr_ports" value="0"/> + <param name="pf_buff_se_rd_ports" value="0"/> + <param name="pf_buff_search_ports" value="1"/> + <param name="wb_buff_rw_ports" value="1"/> + <param name="wb_buff_rd_ports" value="0"/> + <param name="wb_buff_wr_ports" value="0"/> + <param name="wb_buff_se_rd_ports" value="0"/> + <param name="wb_buff_search_ports" value="1"/> + <param name="pure_ram" value="0"/> + <stat name="num_data_array_reads" value="3959"/> + <stat name="num_data_array_writes" value="8086"/> + <stat name="num_tag_array_reads" value="274"/> + <stat name="num_tag_array_writes" value="12046"/> + <stat name="read_misses" value="27"/> + <stat name="write_misses" value="1204"/> + <stat name="conflicts" value="1231"/> + <stat name="duty_cycle" value="1"/> + </component> + </component> + </component> +</component> |