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+// Copyright (c) 2015 ARM Limited
+// All rights reserved.
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+// Copyright 2009-2014 Sandia Coporation.  Under the terms
+// of Contract DE-AC04-94AL85000 with Sandia Corporation, the U.S.
+// Government retains certain rights in this software.
+//
+// Copyright (c) 2009-2014, Sandia Corporation
+// All rights reserved.
+//
+// For license information, see the LICENSE file in the current directory.
+
+#ifndef EXT_SST_EXTMASTER_HH
+#define EXT_SST_EXTMASTER_HH
+
+#include <list>
+#include <set>
+
+#include <sst/core/serialization.h>
+#include <sst/core/component.h>
+#include <sst/elements/memHierarchy/memEvent.h>
+
+#include <sim/sim_object.hh>
+#include <mem/packet.hh>
+#include <mem/request.hh>
+#include <mem/external_master.hh>
+
+namespace SST {
+
+using MemHierarchy::MemEvent;
+class Link;
+class Event;
+
+namespace MemHierarchy {
+class MemNIC;
+}
+
+namespace gem5 {
+
+class gem5Component;
+
+class ExtMaster : public ExternalMaster::Port {
+
+    enum Phase { CONSTRUCTION, INIT, RUN };
+
+    Output& out;
+    const ExternalMaster& port;
+    Phase simPhase;
+
+    gem5Component *const gem5;
+    const std::string name;
+    std::list<PacketPtr> sendQ;
+    bool blocked() { return !sendQ.empty(); }
+
+    MemHierarchy::MemNIC * nic;
+
+    struct SenderState : public Packet::SenderState
+    {
+        MemEvent *event;
+        SenderState(MemEvent* e) : event(e) {}
+    };
+
+    std::set<AddrRange> ranges;
+
+public:
+    bool recvTimingResp(PacketPtr);
+    void recvReqRetry();
+
+    ExtMaster(gem5Component*, Output&, ExternalMaster&, std::string&);
+    void init(unsigned phase);
+    void setup();
+    void finish();
+
+    void clock();
+
+    // receive Requests from SST bound for a gem5 slave;
+    // this module is "external" from gem5's perspective, thus ExternalMaster.
+    void handleEvent(SST::Event*);
+
+protected:
+    virtual void recvRangeChange();
+};
+
+} // namespace gem5
+} // namespace SST
+
+#endif