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-rw-r--r--objects/AlphaConsole.mpy3
-rw-r--r--objects/AlphaTLB.mpy3
-rw-r--r--objects/BadDevice.mpy1
-rw-r--r--objects/BaseCPU.mpy3
-rw-r--r--objects/BaseCache.mpy18
-rw-r--r--objects/BaseSystem.mpy3
-rw-r--r--objects/Bus.mpy1
-rw-r--r--objects/CoherenceProtocol.mpy3
-rw-r--r--objects/Device.mpy6
-rw-r--r--objects/DiskImage.mpy6
-rw-r--r--objects/Ethernet.mpy23
-rw-r--r--objects/Ide.mpy2
-rw-r--r--objects/IntrControl.mpy1
-rw-r--r--objects/MemTest.mpy1
-rw-r--r--objects/Pci.mpy8
-rw-r--r--objects/PhysicalMemory.mpy1
-rw-r--r--objects/Platform.mpy1
-rw-r--r--objects/Process.mpy3
-rw-r--r--objects/Repl.mpy2
-rw-r--r--objects/Root.mpy4
-rw-r--r--objects/SimConsole.mpy6
-rw-r--r--objects/SimpleDisk.mpy1
-rw-r--r--objects/Tsunami.mpy6
-rw-r--r--objects/Uart.mpy1
24 files changed, 80 insertions, 27 deletions
diff --git a/objects/AlphaConsole.mpy b/objects/AlphaConsole.mpy
index bcb47bf8b..79918a01e 100644
--- a/objects/AlphaConsole.mpy
+++ b/objects/AlphaConsole.mpy
@@ -1,8 +1,9 @@
from Device import PioDevice
simobj AlphaConsole(PioDevice):
+ type = 'AlphaConsole'
cpu = Param.BaseCPU(Super, "Processor")
disk = Param.SimpleDisk("Simple Disk")
- num_cpus = Param.Int(1, "Number of CPU's")
+ num_cpus = Param.Int(1, "Number of CPUs")
sim_console = Param.SimConsole(Super, "The Simulator Console")
system = Param.BaseSystem(Super, "system object")
diff --git a/objects/AlphaTLB.mpy b/objects/AlphaTLB.mpy
index 571b98374..8e7cd62cc 100644
--- a/objects/AlphaTLB.mpy
+++ b/objects/AlphaTLB.mpy
@@ -1,9 +1,12 @@
simobj AlphaTLB(SimObject):
+ type = 'AlphaTLB'
abstract = True
size = Param.Int("TLB size")
simobj AlphaDTB(AlphaTLB):
+ type = 'AlphaDTB'
size = 64
simobj AlphaITB(AlphaTLB):
+ type = 'AlphaITB'
size = 48
diff --git a/objects/BadDevice.mpy b/objects/BadDevice.mpy
index 5c56b8036..35a12e0bf 100644
--- a/objects/BadDevice.mpy
+++ b/objects/BadDevice.mpy
@@ -1,4 +1,5 @@
from Device import PioDevice
simobj BadDevice(PioDevice):
+ type = 'BadDevice'
devicename = Param.String("Name of device to error on")
diff --git a/objects/BaseCPU.mpy b/objects/BaseCPU.mpy
index 2aca9120d..f6e6ff96c 100644
--- a/objects/BaseCPU.mpy
+++ b/objects/BaseCPU.mpy
@@ -1,4 +1,5 @@
simobj BaseCPU(SimObject):
+ type = 'BaseCPU'
abstract = True
icache = Param.BaseMem(NULL, "L1 instruction cache object")
dcache = Param.BaseMem(NULL, "L1 data cache object")
@@ -18,7 +19,7 @@ simobj BaseCPU(SimObject):
max_loads_any_thread = Param.Counter(0,
"terminate when any thread reaches this load count")
- defer_registration = Param.Bool(false,
+ defer_registration = Param.Bool(False,
"defer registration with system (for sampling)")
def check(self):
diff --git a/objects/BaseCache.mpy b/objects/BaseCache.mpy
index 67ca3c04e..98a422e30 100644
--- a/objects/BaseCache.mpy
+++ b/objects/BaseCache.mpy
@@ -1,30 +1,38 @@
from BaseMem import BaseMem
simobj BaseCache(BaseMem):
- adaptive_compression = Param.Bool(false,
+ type = 'BaseCache'
+ adaptive_compression = Param.Bool(False,
"Use an adaptive compression scheme")
assoc = Param.Int("associativity")
block_size = Param.Int("block size in bytes")
- compressed_bus = Param.Bool(false,
+ compressed_bus = Param.Bool(False,
"This cache connects to a compressed memory")
compression_latency = Param.Int(0,
"Latency in cycles of compression algorithm")
- do_copy = Param.Bool(false, "perform fast copies in the cache")
+ do_copy = Param.Bool(False, "perform fast copies in the cache")
hash_delay = Param.Int(1, "time in cycles of hash access")
in_bus = Param.Bus(NULL, "incoming bus object")
+ lifo = Param.Bool(False,
+ "whether this NIC partition should use LIFO repl. policy")
max_miss_count = Param.Counter(0,
"number of misses to handle before calling exit")
mshrs = Param.Int("number of MSHRs (max outstanding requests)")
out_bus = Param.Bus("outgoing bus object")
- prioritizeRequests = Param.Bool(false,
+ prioritizeRequests = Param.Bool(False,
"always service demand misses first")
protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
repl = Param.Repl(NULL, "replacement policy")
size = Param.Int("capacity in bytes")
- store_compressed = Param.Bool(false,
+ split = Param.Bool(False, "whether or not this cache is split")
+ split_size = Param.Int(0,
+ "How many ways of the cache belong to CPU/LRU partition")
+ store_compressed = Param.Bool(False,
"Store compressed data in the cache")
subblock_size = Param.Int(0,
"Size of subblock in IIC used for compression")
tgts_per_mshr = Param.Int("max number of accesses per MSHR")
trace_addr = Param.Addr(0, "address to trace")
+ two_queue = Param.Bool(False,
+ "whether the lifo should have two queue replacement")
write_buffers = Param.Int(8, "number of write buffers")
diff --git a/objects/BaseSystem.mpy b/objects/BaseSystem.mpy
index 2a8b98338..1cbdf4e99 100644
--- a/objects/BaseSystem.mpy
+++ b/objects/BaseSystem.mpy
@@ -1,4 +1,5 @@
simobj BaseSystem(SimObject):
+ type = 'BaseSystem'
abstract = True
memctrl = Param.MemoryController(Super, "memory controller")
physmem = Param.PhysicalMemory(Super, "phsyical memory")
@@ -10,5 +11,5 @@ simobj BaseSystem(SimObject):
boot_osflags = Param.String("a", "boot flags to pass to the kernel")
system_type = Param.UInt64("Type of system we are emulating")
system_rev = Param.UInt64("Revision of system we are emulating")
- bin = Param.Bool(false, "is this system binned")
+ bin = Param.Bool(False, "is this system binned")
binned_fns = VectorParam.String([], "functions broken down and binned")
diff --git a/objects/Bus.mpy b/objects/Bus.mpy
index 9e112bfe6..025d69785 100644
--- a/objects/Bus.mpy
+++ b/objects/Bus.mpy
@@ -1,5 +1,6 @@
from BaseHier import BaseHier
simobj Bus(BaseHier):
+ type = 'Bus'
clock_ratio = Param.Int("ratio of CPU to bus frequency")
width = Param.Int("bus width in bytes")
diff --git a/objects/CoherenceProtocol.mpy b/objects/CoherenceProtocol.mpy
index a2518bf39..ae041b638 100644
--- a/objects/CoherenceProtocol.mpy
+++ b/objects/CoherenceProtocol.mpy
@@ -1,5 +1,6 @@
Coherence = Enum('uni', 'msi', 'mesi', 'mosi', 'moesi')
simobj CoherenceProtocol(SimObject):
- do_upgrades = Param.Bool(true, "use upgrade transactions?")
+ type = 'CoherenceProtocol'
+ do_upgrades = Param.Bool(True, "use upgrade transactions?")
protocol = Param.Coherence("name of coherence protocol")
diff --git a/objects/Device.mpy b/objects/Device.mpy
index babc8aa9d..47f8db1cb 100644
--- a/objects/Device.mpy
+++ b/objects/Device.mpy
@@ -11,21 +11,23 @@ from FunctionalMemory import FunctionalMemory
# initialization phase at which point all SimObject pointers will be
# valid.
simobj FooPioDevice(FunctionalMemory):
- abstract = True
type = 'PioDevice'
+ abstract = True
addr = Param.Addr("Device Address")
mmu = Param.MemoryController(Super, "Memory Controller")
io_bus = Param.Bus(NULL, "The IO Bus to attach to")
pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles")
simobj FooDmaDevice(FooPioDevice):
- abstract = True
type = 'DmaDevice'
+ abstract = True
simobj PioDevice(FooPioDevice):
+ type = 'PioDevice'
abstract = True
platform = Param.Platform(Super, "Platform")
simobj DmaDevice(PioDevice):
+ type = 'DmaDevice'
abstract = True
diff --git a/objects/DiskImage.mpy b/objects/DiskImage.mpy
index bea2e56a8..80ef7b072 100644
--- a/objects/DiskImage.mpy
+++ b/objects/DiskImage.mpy
@@ -1,12 +1,14 @@
simobj DiskImage(SimObject):
+ type = 'DiskImage'
abstract = True
image_file = Param.String("disk image file")
- read_only = Param.Bool(false, "read only image")
+ read_only = Param.Bool(False, "read only image")
simobj RawDiskImage(DiskImage):
- pass
+ type = 'RawDiskImage'
simobj CowDiskImage(DiskImage):
+ type = 'CowDiskImage'
child = Param.DiskImage("child image")
table_size = Param.Int(65536, "initial table size")
image_file = ''
diff --git a/objects/Ethernet.mpy b/objects/Ethernet.mpy
index 64eab00a3..088df4b93 100644
--- a/objects/Ethernet.mpy
+++ b/objects/Ethernet.mpy
@@ -2,10 +2,12 @@ from Device import DmaDevice
from Pci import PciDevice
simobj EtherInt(SimObject):
+ type = 'EtherInt'
abstract = True
peer = Param.EtherInt(NULL, "peer interface")
simobj EtherLink(SimObject):
+ type = 'EtherLink'
int1 = Param.EtherInt("interface 1")
int2 = Param.EtherInt("interface 2")
delay = Param.Tick(0, "transmit delay of packets in us")
@@ -13,31 +15,35 @@ simobj EtherLink(SimObject):
dump = Param.EtherDump(NULL, "dump object")
simobj EtherBus(SimObject):
- loopback = Param.Bool(true,
+ type = 'EtherBus'
+ loopback = Param.Bool(True,
"send packet back to the interface from which it came")
dump = Param.EtherDump(NULL, "dump object")
speed = Param.UInt64(100000000, "bus speed in bits per second")
simobj EtherTap(EtherInt):
+ type = 'EtherTap'
bufsz = Param.Int(10000, "tap buffer size")
dump = Param.EtherDump(NULL, "dump object")
port = Param.UInt16(3500, "tap port")
simobj EtherDump(SimObject):
+ type = 'EtherDump'
file = Param.String("dump file")
simobj EtherDev(DmaDevice):
+ type = 'EtherDev'
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
- dma_data_free = Param.Bool(false, "DMA of Data is free")
- dma_desc_free = Param.Bool(false, "DMA of Descriptors is free")
+ dma_data_free = Param.Bool(False, "DMA of Data is free")
+ dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
dma_read_delay = Param.Tick(0, "fixed delay for dma reads")
dma_read_factor = Param.Tick(0, "multiplier for dma reads")
dma_write_delay = Param.Tick(0, "fixed delay for dma writes")
dma_write_factor = Param.Tick(0, "multiplier for dma writes")
- rx_filter = Param.Bool(true, "Enable Receive Filter")
+ rx_filter = Param.Bool(True, "Enable Receive Filter")
rx_delay = Param.Tick(1000, "Receive Delay")
tx_delay = Param.Tick(1000, "Transmit Delay")
@@ -47,17 +53,18 @@ simobj EtherDev(DmaDevice):
tlaser = Param.Turbolaser(Super, "Turbolaser")
simobj NSGigE(PciDevice):
+ type = 'NSGigE'
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
- dma_data_free = Param.Bool(false, "DMA of Data is free")
- dma_desc_free = Param.Bool(false, "DMA of Descriptors is free")
+ dma_data_free = Param.Bool(False, "DMA of Data is free")
+ dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
dma_read_delay = Param.Tick(0, "fixed delay for dma reads")
dma_read_factor = Param.Tick(0, "multiplier for dma reads")
dma_write_delay = Param.Tick(0, "fixed delay for dma writes")
dma_write_factor = Param.Tick(0, "multiplier for dma writes")
- rx_filter = Param.Bool(true, "Enable Receive Filter")
+ rx_filter = Param.Bool(True, "Enable Receive Filter")
rx_delay = Param.Tick(1000, "Receive Delay")
tx_delay = Param.Tick(1000, "Transmit Delay")
@@ -69,9 +76,11 @@ simobj NSGigE(PciDevice):
physmem = Param.PhysicalMemory(Super, "Physical Memory")
simobj EtherDevInt(EtherInt):
+ type = 'EtherDevInt'
device = Param.EtherDev("Ethernet device of this interface")
simobj NSGigEInt(EtherInt):
+ type = 'NSGigEInt'
device = Param.NSGigE("Ethernet device of this interface")
diff --git a/objects/Ide.mpy b/objects/Ide.mpy
index 816b33c8c..c4aa2aca0 100644
--- a/objects/Ide.mpy
+++ b/objects/Ide.mpy
@@ -3,10 +3,12 @@ from Pci import PciDevice
IdeID = Enum('master', 'slave')
simobj IdeDisk(SimObject):
+ type = 'IdeDisk'
delay = Param.Tick(1, "Fixed disk delay in microseconds")
driveID = Param.IdeID('master', "Drive ID")
image = Param.DiskImage("Disk image")
physmem = Param.PhysicalMemory(Super, "Physical memory")
simobj IdeController(PciDevice):
+ type = 'IdeController'
disks = VectorParam.IdeDisk("IDE disks attached to this controller")
diff --git a/objects/IntrControl.mpy b/objects/IntrControl.mpy
index 7c97746ff..1ef5a17ee 100644
--- a/objects/IntrControl.mpy
+++ b/objects/IntrControl.mpy
@@ -1,2 +1,3 @@
simobj IntrControl(SimObject):
+ type = 'IntrControl'
cpu = Param.BaseCPU(Super, "the cpu")
diff --git a/objects/MemTest.mpy b/objects/MemTest.mpy
index 49319e163..1ec33a30c 100644
--- a/objects/MemTest.mpy
+++ b/objects/MemTest.mpy
@@ -1,4 +1,5 @@
simobj MemTest(SimObject):
+ type = 'MemTest'
cache = Param.BaseCache("L1 cache")
check_mem = Param.FunctionalMemory("check memory")
main_mem = Param.FunctionalMemory("hierarchical memory")
diff --git a/objects/Pci.mpy b/objects/Pci.mpy
index d6917b020..caa3c52ff 100644
--- a/objects/Pci.mpy
+++ b/objects/Pci.mpy
@@ -1,7 +1,8 @@
from Device import FooPioDevice, DmaDevice
simobj PciConfigData(FooPioDevice):
- addr = 0xffffffffffffffff
+ type = 'PciConfigData'
+ addr = 0xffffffffffffffffL
VendorID = Param.UInt16("Vendor ID")
DeviceID = Param.UInt16("Device ID")
Command = Param.UInt16(0, "Command")
@@ -38,13 +39,14 @@ simobj PciConfigData(FooPioDevice):
MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
simobj PciConfigAll(FooPioDevice):
- pass
+ type = 'PciConfigAll'
simobj PciDevice(DmaDevice):
+ type = 'PciDevice'
abstract = True
pci_bus = Param.Int("PCI bus")
pci_dev = Param.Int("PCI device number")
pci_func = Param.Int("PCI function code")
configdata = Param.PciConfigData(Super, "PCI Config data")
configspace = Param.PciConfigAll(Super, "PCI Configspace")
- addr = 0xffffffffffffffff
+ addr = 0xffffffffffffffffL
diff --git a/objects/PhysicalMemory.mpy b/objects/PhysicalMemory.mpy
index 9644c503a..d1e4ad4b4 100644
--- a/objects/PhysicalMemory.mpy
+++ b/objects/PhysicalMemory.mpy
@@ -1,6 +1,7 @@
from FunctionalMemory import FunctionalMemory
simobj PhysicalMemory(FunctionalMemory):
+ type = 'PhysicalMemory'
range = Param.AddrRange("Device Address")
file = Param.String('', "memory mapped file")
mmu = Param.MemoryController(Super, "Memory Controller")
diff --git a/objects/Platform.mpy b/objects/Platform.mpy
index 870026259..d0510eaf8 100644
--- a/objects/Platform.mpy
+++ b/objects/Platform.mpy
@@ -1,4 +1,5 @@
simobj Platform(SimObject):
+ type = 'Platform'
abstract = True
interrupt_frequency = Param.Tick(1200, "frequency of interrupts")
intrctrl = Param.IntrControl(Super, "interrupt controller")
diff --git a/objects/Process.mpy b/objects/Process.mpy
index 4f5c4a674..6a91c09c2 100644
--- a/objects/Process.mpy
+++ b/objects/Process.mpy
@@ -1,12 +1,15 @@
simobj Process(SimObject):
+ type = 'Process'
abstract = True
output = Param.String('cout', 'filename for stdout/stderr')
simobj LiveProcess(Process):
+ type = 'LiveProcess'
cmd = VectorParam.String("command line (executable plus arguments)")
env = VectorParam.String('', "environment settings")
input = Param.String('cin', "filename for stdin")
simobj EioProcess(Process):
+ type = 'EioProcess'
chkpt = Param.String('', "EIO checkpoint file name (optional)")
file = Param.String("EIO trace file name")
diff --git a/objects/Repl.mpy b/objects/Repl.mpy
index 87e7bfb7d..fff5a2a02 100644
--- a/objects/Repl.mpy
+++ b/objects/Repl.mpy
@@ -1,7 +1,9 @@
simobj Repl(SimObject):
+ type = 'Repl'
abstract = True
simobj GenRepl(Repl):
+ type = 'GenRepl'
fresh_res = Param.Int("associativity")
num_pools = Param.Int("capacity in bytes")
pool_res = Param.Int("block size in bytes")
diff --git a/objects/Root.mpy b/objects/Root.mpy
index 2649d59fa..b21396e36 100644
--- a/objects/Root.mpy
+++ b/objects/Root.mpy
@@ -1,9 +1,11 @@
from HierParams import HierParams
simobj Root(SimObject):
+ type = 'Root'
frequency = Param.Tick(200000000, "tick frequency")
output_dir = Param.String('.', "directory to output data to")
output_file = Param.String('cout', "file to dump simulator output to")
config_output_file = Param.String('m5config.out',
"file to dump simulator config to")
full_system = Param.Bool("Full system simulation?")
- hier = HierParams(do_data = false, do_events = true)
+ hier = HierParams(do_data = False, do_events = True)
+ checkpoint = Param.String('', "Checkpoint file")
diff --git a/objects/SimConsole.mpy b/objects/SimConsole.mpy
index 0676738f9..ab88db8c6 100644
--- a/objects/SimConsole.mpy
+++ b/objects/SimConsole.mpy
@@ -1,9 +1,11 @@
simobj ConsoleListener(SimObject):
+ type = 'ConsoleListener'
port = Param.UInt16(3456, "listen port")
simobj SimConsole(SimObject):
- append_name = Param.Bool(true, "append name() to filename")
+ type = 'SimConsole'
+ append_name = Param.Bool(True, "append name() to filename")
intr_control = Param.IntrControl(Super, "interrupt controller")
listener = Param.ConsoleListener("console listener")
number = Param.Int(0, "console number")
- output = Param.String("", "file to dump output to")
+ output = Param.String('', "file to dump output to")
diff --git a/objects/SimpleDisk.mpy b/objects/SimpleDisk.mpy
index 46bbdb8fd..c4dd5435b 100644
--- a/objects/SimpleDisk.mpy
+++ b/objects/SimpleDisk.mpy
@@ -1,3 +1,4 @@
simobj SimpleDisk(SimObject):
+ type = 'SimpleDisk'
disk = Param.DiskImage("Disk Image")
physmem = Param.PhysicalMemory(Super, "Physical Memory")
diff --git a/objects/Tsunami.mpy b/objects/Tsunami.mpy
index 6f9555d49..cfe23977e 100644
--- a/objects/Tsunami.mpy
+++ b/objects/Tsunami.mpy
@@ -2,20 +2,24 @@ from Device import FooPioDevice
from Platform import Platform
simobj Tsunami(Platform):
+ type = 'Tsunami'
pciconfig = Param.PciConfigAll("PCI configuration")
system = Param.BaseSystem(Super, "system")
interrupt_frequency = Param.Int(1024, "frequency of interrupts")
simobj TsunamiCChip(FooPioDevice):
+ type = 'TsunamiCChip'
tsunami = Param.Tsunami(Super, "Tsunami")
simobj TsunamiFake(FooPioDevice):
- pass
+ type = 'TsunamiFake'
simobj TsunamiIO(FooPioDevice):
+ type = 'TsunamiIO'
time = Param.UInt64(1136073600,
"System time to use (0 for actual time, default is 1/1/06)")
tsunami = Param.Tsunami(Super, "Tsunami")
simobj TsunamiPChip(FooPioDevice):
+ type = 'TsunamiPChip'
tsunami = Param.Tsunami(Super, "Tsunami")
diff --git a/objects/Uart.mpy b/objects/Uart.mpy
index a54e19dcd..76ee8805f 100644
--- a/objects/Uart.mpy
+++ b/objects/Uart.mpy
@@ -1,5 +1,6 @@
from Device import PioDevice
simobj Uart(PioDevice):
+ type = 'Uart'
console = Param.SimConsole(Super, "The console")
size = Param.Addr(0x8, "Device size")
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 00:07:50 +0000