diff options
Diffstat (limited to 'objects')
| -rw-r--r-- | objects/AlphaConsole.mpy | 8 | ||||
| -rw-r--r-- | objects/AlphaTLB.mpy | 9 | ||||
| -rw-r--r-- | objects/BadDevice.mpy | 4 | ||||
| -rw-r--r-- | objects/BaseCPU.mpy | 38 | ||||
| -rw-r--r-- | objects/BaseCache.mpy | 30 | ||||
| -rw-r--r-- | objects/BaseSystem.mpy | 14 | ||||
| -rw-r--r-- | objects/Bus.mpy | 5 | ||||
| -rw-r--r-- | objects/CoherenceProtocol.mpy | 5 | ||||
| -rw-r--r-- | objects/Device.mpy | 31 | ||||
| -rw-r--r-- | objects/DiskImage.mpy | 12 | ||||
| -rw-r--r-- | objects/Ethernet.mpy | 77 | ||||
| -rw-r--r-- | objects/Ide.mpy | 12 | ||||
| -rw-r--r-- | objects/IntrControl.mpy | 2 | ||||
| -rw-r--r-- | objects/MemTest.mpy | 20 | ||||
| -rw-r--r-- | objects/Pci.mpy | 50 | ||||
| -rw-r--r-- | objects/PhysicalMemory.mpy | 6 | ||||
| -rw-r--r-- | objects/Platform.mpy | 4 | ||||
| -rw-r--r-- | objects/Process.mpy | 12 | ||||
| -rw-r--r-- | objects/Repl.mpy | 7 | ||||
| -rw-r--r-- | objects/Root.mpy | 9 | ||||
| -rw-r--r-- | objects/SimConsole.mpy | 9 | ||||
| -rw-r--r-- | objects/SimpleDisk.mpy | 3 | ||||
| -rw-r--r-- | objects/Tsunami.mpy | 21 | ||||
| -rw-r--r-- | objects/Uart.mpy | 5 |
24 files changed, 393 insertions, 0 deletions
diff --git a/objects/AlphaConsole.mpy b/objects/AlphaConsole.mpy new file mode 100644 index 000000000..bcb47bf8b --- /dev/null +++ b/objects/AlphaConsole.mpy @@ -0,0 +1,8 @@ +from Device import PioDevice + +simobj AlphaConsole(PioDevice): + cpu = Param.BaseCPU(Super, "Processor") + disk = Param.SimpleDisk("Simple Disk") + num_cpus = Param.Int(1, "Number of CPU's") + sim_console = Param.SimConsole(Super, "The Simulator Console") + system = Param.BaseSystem(Super, "system object") diff --git a/objects/AlphaTLB.mpy b/objects/AlphaTLB.mpy new file mode 100644 index 000000000..571b98374 --- /dev/null +++ b/objects/AlphaTLB.mpy @@ -0,0 +1,9 @@ +simobj AlphaTLB(SimObject): + abstract = True + size = Param.Int("TLB size") + +simobj AlphaDTB(AlphaTLB): + size = 64 + +simobj AlphaITB(AlphaTLB): + size = 48 diff --git a/objects/BadDevice.mpy b/objects/BadDevice.mpy new file mode 100644 index 000000000..5c56b8036 --- /dev/null +++ b/objects/BadDevice.mpy @@ -0,0 +1,4 @@ +from Device import PioDevice + +simobj BadDevice(PioDevice): + devicename = Param.String("Name of device to error on") diff --git a/objects/BaseCPU.mpy b/objects/BaseCPU.mpy new file mode 100644 index 000000000..2aca9120d --- /dev/null +++ b/objects/BaseCPU.mpy @@ -0,0 +1,38 @@ +simobj BaseCPU(SimObject): + abstract = True + icache = Param.BaseMem(NULL, "L1 instruction cache object") + dcache = Param.BaseMem(NULL, "L1 data cache object") + + dtb = Param.AlphaDTB("Data TLB") + itb = Param.AlphaITB("Instruction TLB") + mem = Param.FunctionalMemory("memory") + system = Param.BaseSystem(Super, "system object") + workload = VectorParam.Process("processes to run") + + max_insts_all_threads = Param.Counter(0, + "terminate when all threads have reached this inst count") + max_insts_any_thread = Param.Counter(0, + "terminate when any thread reaches this inst count") + max_loads_all_threads = Param.Counter(0, + "terminate when all threads have reached this load count") + max_loads_any_thread = Param.Counter(0, + "terminate when any thread reaches this load count") + + defer_registration = Param.Bool(false, + "defer registration with system (for sampling)") + + def check(self): + has_workload = self._hasvalue('workload') + has_dtb = self._hasvalue('dtb') + has_itb = self._hasvalue('itb') + has_mem = self._hasvalue('mem') + has_system = self._hasvalue('system') + + if has_workload: + self.dtb.disable = True + self.itb.disable = True + self.mem.disable = True + self.system.disable = True + + if has_dtb or has_itb or has_mem or has_system: + self.workload.disable = True diff --git a/objects/BaseCache.mpy b/objects/BaseCache.mpy new file mode 100644 index 000000000..67ca3c04e --- /dev/null +++ b/objects/BaseCache.mpy @@ -0,0 +1,30 @@ +from BaseMem import BaseMem + +simobj BaseCache(BaseMem): + adaptive_compression = Param.Bool(false, + "Use an adaptive compression scheme") + assoc = Param.Int("associativity") + block_size = Param.Int("block size in bytes") + compressed_bus = Param.Bool(false, + "This cache connects to a compressed memory") + compression_latency = Param.Int(0, + "Latency in cycles of compression algorithm") + do_copy = Param.Bool(false, "perform fast copies in the cache") + hash_delay = Param.Int(1, "time in cycles of hash access") + in_bus = Param.Bus(NULL, "incoming bus object") + max_miss_count = Param.Counter(0, + "number of misses to handle before calling exit") + mshrs = Param.Int("number of MSHRs (max outstanding requests)") + out_bus = Param.Bus("outgoing bus object") + prioritizeRequests = Param.Bool(false, + "always service demand misses first") + protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use") + repl = Param.Repl(NULL, "replacement policy") + size = Param.Int("capacity in bytes") + store_compressed = Param.Bool(false, + "Store compressed data in the cache") + subblock_size = Param.Int(0, + "Size of subblock in IIC used for compression") + tgts_per_mshr = Param.Int("max number of accesses per MSHR") + trace_addr = Param.Addr(0, "address to trace") + write_buffers = Param.Int(8, "number of write buffers") diff --git a/objects/BaseSystem.mpy b/objects/BaseSystem.mpy new file mode 100644 index 000000000..2a8b98338 --- /dev/null +++ b/objects/BaseSystem.mpy @@ -0,0 +1,14 @@ +simobj BaseSystem(SimObject): + abstract = True + memctrl = Param.MemoryController(Super, "memory controller") + physmem = Param.PhysicalMemory(Super, "phsyical memory") + kernel = Param.String("file that contains the kernel code") + console = Param.String("file that contains the console code") + pal = Param.String("file that contains palcode") + readfile = Param.String("", "file to read startup script from") + init_param = Param.UInt64(0, "numerical value to pass into simulator") + boot_osflags = Param.String("a", "boot flags to pass to the kernel") + system_type = Param.UInt64("Type of system we are emulating") + system_rev = Param.UInt64("Revision of system we are emulating") + bin = Param.Bool(false, "is this system binned") + binned_fns = VectorParam.String([], "functions broken down and binned") diff --git a/objects/Bus.mpy b/objects/Bus.mpy new file mode 100644 index 000000000..9e112bfe6 --- /dev/null +++ b/objects/Bus.mpy @@ -0,0 +1,5 @@ +from BaseHier import BaseHier + +simobj Bus(BaseHier): + clock_ratio = Param.Int("ratio of CPU to bus frequency") + width = Param.Int("bus width in bytes") diff --git a/objects/CoherenceProtocol.mpy b/objects/CoherenceProtocol.mpy new file mode 100644 index 000000000..a2518bf39 --- /dev/null +++ b/objects/CoherenceProtocol.mpy @@ -0,0 +1,5 @@ +Coherence = Enum('uni', 'msi', 'mesi', 'mosi', 'moesi') + +simobj CoherenceProtocol(SimObject): + do_upgrades = Param.Bool(true, "use upgrade transactions?") + protocol = Param.Coherence("name of coherence protocol") diff --git a/objects/Device.mpy b/objects/Device.mpy new file mode 100644 index 000000000..babc8aa9d --- /dev/null +++ b/objects/Device.mpy @@ -0,0 +1,31 @@ +from FunctionalMemory import FunctionalMemory + +# This device exists only because there are some devices that I don't +# want to have a Platform parameter because it would cause a cycle in +# the C++ that cannot be easily solved. +# +# The real solution to this problem is to pass the ParamXXX structure +# to the constructor, but with the express condition that SimObject +# parameter values are not to be available at construction time. If +# some further configuration must be done, it must be done during the +# initialization phase at which point all SimObject pointers will be +# valid. +simobj FooPioDevice(FunctionalMemory): + abstract = True + type = 'PioDevice' + addr = Param.Addr("Device Address") + mmu = Param.MemoryController(Super, "Memory Controller") + io_bus = Param.Bus(NULL, "The IO Bus to attach to") + pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles") + +simobj FooDmaDevice(FooPioDevice): + abstract = True + type = 'DmaDevice' + +simobj PioDevice(FooPioDevice): + abstract = True + platform = Param.Platform(Super, "Platform") + +simobj DmaDevice(PioDevice): + abstract = True + diff --git a/objects/DiskImage.mpy b/objects/DiskImage.mpy new file mode 100644 index 000000000..bea2e56a8 --- /dev/null +++ b/objects/DiskImage.mpy @@ -0,0 +1,12 @@ +simobj DiskImage(SimObject): + abstract = True + image_file = Param.String("disk image file") + read_only = Param.Bool(false, "read only image") + +simobj RawDiskImage(DiskImage): + pass + +simobj CowDiskImage(DiskImage): + child = Param.DiskImage("child image") + table_size = Param.Int(65536, "initial table size") + image_file = '' diff --git a/objects/Ethernet.mpy b/objects/Ethernet.mpy new file mode 100644 index 000000000..64eab00a3 --- /dev/null +++ b/objects/Ethernet.mpy @@ -0,0 +1,77 @@ +from Device import DmaDevice +from Pci import PciDevice + +simobj EtherInt(SimObject): + abstract = True + peer = Param.EtherInt(NULL, "peer interface") + +simobj EtherLink(SimObject): + int1 = Param.EtherInt("interface 1") + int2 = Param.EtherInt("interface 2") + delay = Param.Tick(0, "transmit delay of packets in us") + speed = Param.Tick(100000000, "link speed in bits per second") + dump = Param.EtherDump(NULL, "dump object") + +simobj EtherBus(SimObject): + loopback = Param.Bool(true, + "send packet back to the interface from which it came") + dump = Param.EtherDump(NULL, "dump object") + speed = Param.UInt64(100000000, "bus speed in bits per second") + +simobj EtherTap(EtherInt): + bufsz = Param.Int(10000, "tap buffer size") + dump = Param.EtherDump(NULL, "dump object") + port = Param.UInt16(3500, "tap port") + +simobj EtherDump(SimObject): + file = Param.String("dump file") + +simobj EtherDev(DmaDevice): + hardware_address = Param.EthernetAddr(NextEthernetAddr, + "Ethernet Hardware Address") + + dma_data_free = Param.Bool(false, "DMA of Data is free") + dma_desc_free = Param.Bool(false, "DMA of Descriptors is free") + dma_read_delay = Param.Tick(0, "fixed delay for dma reads") + dma_read_factor = Param.Tick(0, "multiplier for dma reads") + dma_write_delay = Param.Tick(0, "fixed delay for dma writes") + dma_write_factor = Param.Tick(0, "multiplier for dma writes") + + rx_filter = Param.Bool(true, "Enable Receive Filter") + rx_delay = Param.Tick(1000, "Receive Delay") + tx_delay = Param.Tick(1000, "Transmit Delay") + + intr_delay = Param.Tick(0, "Interrupt Delay in microseconds") + payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") + physmem = Param.PhysicalMemory(Super, "Physical Memory") + tlaser = Param.Turbolaser(Super, "Turbolaser") + +simobj NSGigE(PciDevice): + hardware_address = Param.EthernetAddr(NextEthernetAddr, + "Ethernet Hardware Address") + + dma_data_free = Param.Bool(false, "DMA of Data is free") + dma_desc_free = Param.Bool(false, "DMA of Descriptors is free") + dma_read_delay = Param.Tick(0, "fixed delay for dma reads") + dma_read_factor = Param.Tick(0, "multiplier for dma reads") + dma_write_delay = Param.Tick(0, "fixed delay for dma writes") + dma_write_factor = Param.Tick(0, "multiplier for dma writes") + + rx_filter = Param.Bool(true, "Enable Receive Filter") + rx_delay = Param.Tick(1000, "Receive Delay") + tx_delay = Param.Tick(1000, "Transmit Delay") + + rx_fifo_size = Param.Int(131072, "max size in bytes of rxFifo") + tx_fifo_size = Param.Int(131072, "max size in bytes of txFifo") + + intr_delay = Param.Tick(0, "Interrupt Delay in microseconds") + payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") + physmem = Param.PhysicalMemory(Super, "Physical Memory") + +simobj EtherDevInt(EtherInt): + device = Param.EtherDev("Ethernet device of this interface") + +simobj NSGigEInt(EtherInt): + device = Param.NSGigE("Ethernet device of this interface") + + diff --git a/objects/Ide.mpy b/objects/Ide.mpy new file mode 100644 index 000000000..816b33c8c --- /dev/null +++ b/objects/Ide.mpy @@ -0,0 +1,12 @@ +from Pci import PciDevice + +IdeID = Enum('master', 'slave') + +simobj IdeDisk(SimObject): + delay = Param.Tick(1, "Fixed disk delay in microseconds") + driveID = Param.IdeID('master', "Drive ID") + image = Param.DiskImage("Disk image") + physmem = Param.PhysicalMemory(Super, "Physical memory") + +simobj IdeController(PciDevice): + disks = VectorParam.IdeDisk("IDE disks attached to this controller") diff --git a/objects/IntrControl.mpy b/objects/IntrControl.mpy new file mode 100644 index 000000000..7c97746ff --- /dev/null +++ b/objects/IntrControl.mpy @@ -0,0 +1,2 @@ +simobj IntrControl(SimObject): + cpu = Param.BaseCPU(Super, "the cpu") diff --git a/objects/MemTest.mpy b/objects/MemTest.mpy new file mode 100644 index 000000000..49319e163 --- /dev/null +++ b/objects/MemTest.mpy @@ -0,0 +1,20 @@ +simobj MemTest(SimObject): + cache = Param.BaseCache("L1 cache") + check_mem = Param.FunctionalMemory("check memory") + main_mem = Param.FunctionalMemory("hierarchical memory") + max_loads_all_threads = Param.Counter(0, + "terminate when all threads have reached this load count") + max_loads_any_thread = Param.Counter(0, + "terminate when any thread reaches this load count") + memory_size = Param.Int(65536, "memory size") + percent_copies = Param.Percent(0, "target copy percentage") + percent_dest_unaligned = Param.Percent(50, + "percent of copy dest address that are unaligned") + percent_reads = Param.Percent(65, "target read percentage") + percent_source_unaligned = Param.Percent(50, + "percent of copy source address that are unaligned") + percent_uncacheable = Param.Percent(10, + "target uncacheable percentage") + progress_interval = Param.Counter(1000000, + "progress report interval (in accesses)") + trace_addr = Param.Addr(0, "address to trace") diff --git a/objects/Pci.mpy b/objects/Pci.mpy new file mode 100644 index 000000000..d6917b020 --- /dev/null +++ b/objects/Pci.mpy @@ -0,0 +1,50 @@ +from Device import FooPioDevice, DmaDevice + +simobj PciConfigData(FooPioDevice): + addr = 0xffffffffffffffff + VendorID = Param.UInt16("Vendor ID") + DeviceID = Param.UInt16("Device ID") + Command = Param.UInt16(0, "Command") + Status = Param.UInt16(0, "Status") + Revision = Param.UInt8(0, "Device") + ProgIF = Param.UInt8(0, "Programming Interface") + SubClassCode = Param.UInt8(0, "Sub-Class Code") + ClassCode = Param.UInt8(0, "Class Code") + CacheLineSize = Param.UInt8(0, "System Cacheline Size") + LatencyTimer = Param.UInt8(0, "PCI Latency Timer") + HeaderType = Param.UInt8(0, "PCI Header Type") + BIST = Param.UInt8(0, "Built In Self Test") + + BAR0 = Param.UInt32(0x00, "Base Address Register 0") + BAR1 = Param.UInt32(0x00, "Base Address Register 1") + BAR2 = Param.UInt32(0x00, "Base Address Register 2") + BAR3 = Param.UInt32(0x00, "Base Address Register 3") + BAR4 = Param.UInt32(0x00, "Base Address Register 4") + BAR5 = Param.UInt32(0x00, "Base Address Register 5") + BAR0Size = Param.UInt32(0, "Base Address Register 0 Size") + BAR1Size = Param.UInt32(0, "Base Address Register 1 Size") + BAR2Size = Param.UInt32(0, "Base Address Register 2 Size") + BAR3Size = Param.UInt32(0, "Base Address Register 3 Size") + BAR4Size = Param.UInt32(0, "Base Address Register 4 Size") + BAR5Size = Param.UInt32(0, "Base Address Register 5 Size") + + CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure") + SubsystemID = Param.UInt16(0x00, "Subsystem ID") + SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID") + ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address") + InterruptLine = Param.UInt8(0x00, "Interrupt Line") + InterruptPin = Param.UInt8(0x00, "Interrupt Pin") + MaximumLatency = Param.UInt8(0x00, "Maximum Latency") + MinimumGrant = Param.UInt8(0x00, "Minimum Grant") + +simobj PciConfigAll(FooPioDevice): + pass + +simobj PciDevice(DmaDevice): + abstract = True + pci_bus = Param.Int("PCI bus") + pci_dev = Param.Int("PCI device number") + pci_func = Param.Int("PCI function code") + configdata = Param.PciConfigData(Super, "PCI Config data") + configspace = Param.PciConfigAll(Super, "PCI Configspace") + addr = 0xffffffffffffffff diff --git a/objects/PhysicalMemory.mpy b/objects/PhysicalMemory.mpy new file mode 100644 index 000000000..9644c503a --- /dev/null +++ b/objects/PhysicalMemory.mpy @@ -0,0 +1,6 @@ +from FunctionalMemory import FunctionalMemory + +simobj PhysicalMemory(FunctionalMemory): + range = Param.AddrRange("Device Address") + file = Param.String('', "memory mapped file") + mmu = Param.MemoryController(Super, "Memory Controller") diff --git a/objects/Platform.mpy b/objects/Platform.mpy new file mode 100644 index 000000000..870026259 --- /dev/null +++ b/objects/Platform.mpy @@ -0,0 +1,4 @@ +simobj Platform(SimObject): + abstract = True + interrupt_frequency = Param.Tick(1200, "frequency of interrupts") + intrctrl = Param.IntrControl(Super, "interrupt controller") diff --git a/objects/Process.mpy b/objects/Process.mpy new file mode 100644 index 000000000..4f5c4a674 --- /dev/null +++ b/objects/Process.mpy @@ -0,0 +1,12 @@ +simobj Process(SimObject): + abstract = True + output = Param.String('cout', 'filename for stdout/stderr') + +simobj LiveProcess(Process): + cmd = VectorParam.String("command line (executable plus arguments)") + env = VectorParam.String('', "environment settings") + input = Param.String('cin', "filename for stdin") + +simobj EioProcess(Process): + chkpt = Param.String('', "EIO checkpoint file name (optional)") + file = Param.String("EIO trace file name") diff --git a/objects/Repl.mpy b/objects/Repl.mpy new file mode 100644 index 000000000..87e7bfb7d --- /dev/null +++ b/objects/Repl.mpy @@ -0,0 +1,7 @@ +simobj Repl(SimObject): + abstract = True + +simobj GenRepl(Repl): + fresh_res = Param.Int("associativity") + num_pools = Param.Int("capacity in bytes") + pool_res = Param.Int("block size in bytes") diff --git a/objects/Root.mpy b/objects/Root.mpy new file mode 100644 index 000000000..2649d59fa --- /dev/null +++ b/objects/Root.mpy @@ -0,0 +1,9 @@ +from HierParams import HierParams +simobj Root(SimObject): + frequency = Param.Tick(200000000, "tick frequency") + output_dir = Param.String('.', "directory to output data to") + output_file = Param.String('cout', "file to dump simulator output to") + config_output_file = Param.String('m5config.out', + "file to dump simulator config to") + full_system = Param.Bool("Full system simulation?") + hier = HierParams(do_data = false, do_events = true) diff --git a/objects/SimConsole.mpy b/objects/SimConsole.mpy new file mode 100644 index 000000000..0676738f9 --- /dev/null +++ b/objects/SimConsole.mpy @@ -0,0 +1,9 @@ +simobj ConsoleListener(SimObject): + port = Param.UInt16(3456, "listen port") + +simobj SimConsole(SimObject): + append_name = Param.Bool(true, "append name() to filename") + intr_control = Param.IntrControl(Super, "interrupt controller") + listener = Param.ConsoleListener("console listener") + number = Param.Int(0, "console number") + output = Param.String("", "file to dump output to") diff --git a/objects/SimpleDisk.mpy b/objects/SimpleDisk.mpy new file mode 100644 index 000000000..46bbdb8fd --- /dev/null +++ b/objects/SimpleDisk.mpy @@ -0,0 +1,3 @@ +simobj SimpleDisk(SimObject): + disk = Param.DiskImage("Disk Image") + physmem = Param.PhysicalMemory(Super, "Physical Memory") diff --git a/objects/Tsunami.mpy b/objects/Tsunami.mpy new file mode 100644 index 000000000..6f9555d49 --- /dev/null +++ b/objects/Tsunami.mpy @@ -0,0 +1,21 @@ +from Device import FooPioDevice +from Platform import Platform + +simobj Tsunami(Platform): + pciconfig = Param.PciConfigAll("PCI configuration") + system = Param.BaseSystem(Super, "system") + interrupt_frequency = Param.Int(1024, "frequency of interrupts") + +simobj TsunamiCChip(FooPioDevice): + tsunami = Param.Tsunami(Super, "Tsunami") + +simobj TsunamiFake(FooPioDevice): + pass + +simobj TsunamiIO(FooPioDevice): + time = Param.UInt64(1136073600, + "System time to use (0 for actual time, default is 1/1/06)") + tsunami = Param.Tsunami(Super, "Tsunami") + +simobj TsunamiPChip(FooPioDevice): + tsunami = Param.Tsunami(Super, "Tsunami") diff --git a/objects/Uart.mpy b/objects/Uart.mpy new file mode 100644 index 000000000..a54e19dcd --- /dev/null +++ b/objects/Uart.mpy @@ -0,0 +1,5 @@ +from Device import PioDevice + +simobj Uart(PioDevice): + console = Param.SimConsole(Super, "The console") + size = Param.Addr(0x8, "Device size") |