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-rw-r--r--python/m5/objects/BaseCPU.mpy2
1 files changed, 1 insertions, 1 deletions
diff --git a/python/m5/objects/BaseCPU.mpy b/python/m5/objects/BaseCPU.mpy
index be93e8ad1..5d8305d88 100644
--- a/python/m5/objects/BaseCPU.mpy
+++ b/python/m5/objects/BaseCPU.mpy
@@ -4,7 +4,7 @@ simobj BaseCPU(SimObject):
icache = Param.BaseMem(NULL, "L1 instruction cache object")
dcache = Param.BaseMem(NULL, "L1 data cache object")
- if env.get('FULL_SYSTEM', 'False'):
+ if build_env['FULL_SYSTEM']:
dtb = Param.AlphaDTB("Data TLB")
itb = Param.AlphaITB("Instruction TLB")
mem = Param.FunctionalMemory("memory")