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Diffstat (limited to 'python/m5/objects/BaseCPU.py')
| -rw-r--r-- | python/m5/objects/BaseCPU.py | 29 |
1 files changed, 0 insertions, 29 deletions
diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py deleted file mode 100644 index a90203729..000000000 --- a/python/m5/objects/BaseCPU.py +++ /dev/null @@ -1,29 +0,0 @@ -from m5 import * -class BaseCPU(SimObject): - type = 'BaseCPU' - abstract = True - icache = Param.BaseMem(NULL, "L1 instruction cache object") - dcache = Param.BaseMem(NULL, "L1 data cache object") - - if build_env['FULL_SYSTEM']: - dtb = Param.AlphaDTB("Data TLB") - itb = Param.AlphaITB("Instruction TLB") - mem = Param.FunctionalMemory("memory") - system = Param.System(Parent.any, "system object") - cpu_id = Param.Int(-1, "CPU identifier") - else: - workload = VectorParam.Process("processes to run") - - max_insts_all_threads = Param.Counter(0, - "terminate when all threads have reached this inst count") - max_insts_any_thread = Param.Counter(0, - "terminate when any thread reaches this inst count") - max_loads_all_threads = Param.Counter(0, - "terminate when all threads have reached this load count") - max_loads_any_thread = Param.Counter(0, - "terminate when any thread reaches this load count") - - defer_registration = Param.Bool(False, - "defer registration with system (for sampling)") - - clock = Param.Clock(Parent.clock, "clock speed") |