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Diffstat (limited to 'python/m5/objects/BaseCPU.py')
| -rw-r--r-- | python/m5/objects/BaseCPU.py | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py new file mode 100644 index 000000000..d4fa13d3b --- /dev/null +++ b/python/m5/objects/BaseCPU.py @@ -0,0 +1,28 @@ +from m5 import * +class BaseCPU(SimObject): + type = 'BaseCPU' + abstract = True + icache = Param.BaseMem(NULL, "L1 instruction cache object") + dcache = Param.BaseMem(NULL, "L1 data cache object") + + if build_env['FULL_SYSTEM']: + dtb = Param.AlphaDTB("Data TLB") + itb = Param.AlphaITB("Instruction TLB") + mem = Param.FunctionalMemory("memory") + system = Param.BaseSystem(Parent.any, "system object") + else: + workload = VectorParam.Process("processes to run") + + max_insts_all_threads = Param.Counter(0, + "terminate when all threads have reached this inst count") + max_insts_any_thread = Param.Counter(0, + "terminate when any thread reaches this inst count") + max_loads_all_threads = Param.Counter(0, + "terminate when all threads have reached this load count") + max_loads_any_thread = Param.Counter(0, + "terminate when any thread reaches this load count") + + defer_registration = Param.Bool(False, + "defer registration with system (for sampling)") + + cycle_time = Param.Latency(Parent.frequency.latency, "clock speed") |