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-rw-r--r--python/m5/objects/BaseCPU.py2
1 files changed, 0 insertions, 2 deletions
diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py
index fac452285..e5e43022f 100644
--- a/python/m5/objects/BaseCPU.py
+++ b/python/m5/objects/BaseCPU.py
@@ -2,8 +2,6 @@ from m5 import *
class BaseCPU(SimObject):
type = 'BaseCPU'
abstract = True
- icache = Param.BaseMem(NULL, "L1 instruction cache object")
- dcache = Param.BaseMem(NULL, "L1 data cache object")
if build_env['FULL_SYSTEM']:
dtb = Param.AlphaDTB("Data TLB")