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Diffstat (limited to 'python/m5/objects/BaseCache.mpy')
| -rw-r--r-- | python/m5/objects/BaseCache.mpy | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy index 98a422e30..b9986917f 100644 --- a/python/m5/objects/BaseCache.mpy +++ b/python/m5/objects/BaseCache.mpy @@ -23,7 +23,7 @@ simobj BaseCache(BaseMem): "always service demand misses first") protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use") repl = Param.Repl(NULL, "replacement policy") - size = Param.Int("capacity in bytes") + size = Param.MemorySize("capacity in bytes") split = Param.Bool(False, "whether or not this cache is split") split_size = Param.Int(0, "How many ways of the cache belong to CPU/LRU partition") |