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Diffstat (limited to 'python/m5/objects/Ethernet.py')
| -rw-r--r-- | python/m5/objects/Ethernet.py | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py index 68b21b404..4286c71c8 100644 --- a/python/m5/objects/Ethernet.py +++ b/python/m5/objects/Ethernet.py @@ -67,15 +67,10 @@ class EtherDevBase(PciDevice): clock = Param.Clock('0ns', "State machine processor frequency") - physmem = Param.PhysicalMemory(Parent.any, "Physical Memory") - - hier = Param.HierParams(Parent.any, "Hierarchy global variables") - payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") dma_read_factor = Param.Latency('0us', "multiplier for dma reads") dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") dma_write_factor = Param.Latency('0us', "multiplier for dma writes") - dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") rx_delay = Param.Latency('1us', "Receive Delay") tx_delay = Param.Latency('1us', "Transmit Delay") @@ -93,6 +88,7 @@ class NSGigE(EtherDevBase): dma_data_free = Param.Bool(False, "DMA of Data is free") dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") + dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") class NSGigEInt(EtherInt): |