diff options
Diffstat (limited to 'python/m5/objects')
-rw-r--r-- | python/m5/objects/AlphaFullCPU.py | 2 | ||||
-rw-r--r-- | python/m5/objects/OzoneCPU.py | 4 |
2 files changed, 6 insertions, 0 deletions
diff --git a/python/m5/objects/AlphaFullCPU.py b/python/m5/objects/AlphaFullCPU.py index 015e9d872..5b6fa1063 100644 --- a/python/m5/objects/AlphaFullCPU.py +++ b/python/m5/objects/AlphaFullCPU.py @@ -10,6 +10,8 @@ class DerivAlphaFullCPU(BaseCPU): mem = Param.FunctionalMemory(NULL, "memory") checker = Param.BaseCPU(NULL, "checker") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") cachePorts = Param.Unsigned("Cache Ports") diff --git a/python/m5/objects/OzoneCPU.py b/python/m5/objects/OzoneCPU.py index ea8b6b537..dadca7990 100644 --- a/python/m5/objects/OzoneCPU.py +++ b/python/m5/objects/OzoneCPU.py @@ -10,9 +10,12 @@ class DerivOzoneCPU(BaseCPU): mem = Param.FunctionalMemory(NULL, "memory") checker = Param.BaseCPU("Checker CPU") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") width = Param.Unsigned("Width") frontEndWidth = Param.Unsigned("Front end width") + frontEndLatency = Param.Unsigned("Front end latency") backEndWidth = Param.Unsigned("Back end width") backEndSquashLatency = Param.Unsigned("Back end squash latency") backEndLatency = Param.Unsigned("Back end latency") @@ -75,6 +78,7 @@ class DerivOzoneCPU(BaseCPU): LQEntries = Param.Unsigned("Number of load queue entries") SQEntries = Param.Unsigned("Number of store queue entries") + lsqLimits = Param.Bool(True, "LSQ size limits dispatch") LFSTSize = Param.Unsigned("Last fetched store table size") SSITSize = Param.Unsigned("Store set ID table size") |