diff options
Diffstat (limited to 'python/m5/objects')
| -rw-r--r-- | python/m5/objects/BaseCache.mpy | 22 | ||||
| -rw-r--r-- | python/m5/objects/Root.mpy | 1 | ||||
| -rw-r--r-- | python/m5/objects/SimConsole.mpy | 2 |
3 files changed, 23 insertions, 2 deletions
diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy index b9986917f..214e0555c 100644 --- a/python/m5/objects/BaseCache.mpy +++ b/python/m5/objects/BaseCache.mpy @@ -1,5 +1,7 @@ from BaseMem import BaseMem +class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb'] + simobj BaseCache(BaseMem): type = 'BaseCache' adaptive_compression = Param.Bool(False, @@ -36,3 +38,23 @@ simobj BaseCache(BaseMem): two_queue = Param.Bool(False, "whether the lifo should have two queue replacement") write_buffers = Param.Int(8, "number of write buffers") + prefetch_miss = Param.Bool(False, + "wheter you are using the hardware prefetcher from Miss stream") + prefetch_access = Param.Bool(False, + "wheter you are using the hardware prefetcher from Access stream") + prefetcher_size = Param.Int(100, + "Number of entries in the harware prefetch queue") + prefetch_past_page = Param.Bool(False, + "Allow prefetches to cross virtual page boundaries") + prefetch_serial_squash = Param.Bool(False, + "Squash prefetches with a later time on a subsequent miss") + prefetch_degree = Param.Int(1, + "Degree of the prefetch depth") + prefetch_latency = Param.Tick(10, + "Latency of the prefetcher") + prefetch_policy = Param.Prefetch('none', + "Type of prefetcher to use") + prefetch_cache_check_push = Param.Bool(True, + "Check if in cash on push or pop of prefetch queue") + prefetch_use_cpu_id = Param.Bool(True, + "Use the CPU ID to seperate calculations of prefetches") diff --git a/python/m5/objects/Root.mpy b/python/m5/objects/Root.mpy index c535bd2dc..2493dc4ff 100644 --- a/python/m5/objects/Root.mpy +++ b/python/m5/objects/Root.mpy @@ -7,7 +7,6 @@ simobj Root(SimObject): type = 'Root' frequency = Param.RootFrequency('200MHz', "tick frequency") output_file = Param.String('cout', "file to dump simulator output to") - full_system = Param.Bool("Full system simulation?") hier = HierParams(do_data = False, do_events = True) checkpoint = Param.String('', "Checkpoint file") stats = Statistics() diff --git a/python/m5/objects/SimConsole.mpy b/python/m5/objects/SimConsole.mpy index 3588a949d..53ddaa25c 100644 --- a/python/m5/objects/SimConsole.mpy +++ b/python/m5/objects/SimConsole.mpy @@ -1,6 +1,6 @@ simobj ConsoleListener(SimObject): type = 'ConsoleListener' - port = Param.UInt16(3456, "listen port") + port = Param.TcpPort(3456, "listen port") simobj SimConsole(SimObject): type = 'SimConsole' |