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-rw-r--r--python/m5/objects/BaseCPU.mpy2
-rw-r--r--python/m5/objects/BaseCache.mpy4
-rw-r--r--python/m5/objects/BaseSystem.mpy2
-rw-r--r--python/m5/objects/Ethernet.mpy39
-rw-r--r--python/m5/objects/Ide.mpy2
-rw-r--r--python/m5/objects/Platform.mpy1
-rw-r--r--python/m5/objects/Tsunami.mpy2
7 files changed, 29 insertions, 23 deletions
diff --git a/python/m5/objects/BaseCPU.mpy b/python/m5/objects/BaseCPU.mpy
index d84e30e53..707d1b94f 100644
--- a/python/m5/objects/BaseCPU.mpy
+++ b/python/m5/objects/BaseCPU.mpy
@@ -23,3 +23,5 @@ simobj BaseCPU(SimObject):
defer_registration = Param.Bool(False,
"defer registration with system (for sampling)")
+
+ cycle_time = Param.ClockPeriod(parent.frequency, "clock speed")
diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy
index 214e0555c..da0c7c50e 100644
--- a/python/m5/objects/BaseCache.mpy
+++ b/python/m5/objects/BaseCache.mpy
@@ -10,7 +10,7 @@ simobj BaseCache(BaseMem):
block_size = Param.Int("block size in bytes")
compressed_bus = Param.Bool(False,
"This cache connects to a compressed memory")
- compression_latency = Param.Int(0,
+ compression_latency = Param.Latency('0c',
"Latency in cycles of compression algorithm")
do_copy = Param.Bool(False, "perform fast copies in the cache")
hash_delay = Param.Int(1, "time in cycles of hash access")
@@ -58,3 +58,5 @@ simobj BaseCache(BaseMem):
"Check if in cash on push or pop of prefetch queue")
prefetch_use_cpu_id = Param.Bool(True,
"Use the CPU ID to seperate calculations of prefetches")
+ prefetch_data_accesses_only = Param.Bool(False,
+ "Only prefetch on data not on instruction accesses")
diff --git a/python/m5/objects/BaseSystem.mpy b/python/m5/objects/BaseSystem.mpy
index 450b6a58e..29fe3e1d9 100644
--- a/python/m5/objects/BaseSystem.mpy
+++ b/python/m5/objects/BaseSystem.mpy
@@ -1,6 +1,8 @@
simobj BaseSystem(SimObject):
type = 'BaseSystem'
abstract = True
+ boot_cpu_frequency = Param.ClockPeriod(parent.cpu[0].cycle_time,
+ "Boot Processor Frequency")
memctrl = Param.MemoryController(parent.any, "memory controller")
physmem = Param.PhysicalMemory(parent.any, "phsyical memory")
kernel = Param.String("file that contains the kernel code")
diff --git a/python/m5/objects/Ethernet.mpy b/python/m5/objects/Ethernet.mpy
index 3acd8d04d..ed95ce233 100644
--- a/python/m5/objects/Ethernet.mpy
+++ b/python/m5/objects/Ethernet.mpy
@@ -10,16 +10,15 @@ simobj EtherLink(SimObject):
type = 'EtherLink'
int1 = Param.EtherInt("interface 1")
int2 = Param.EtherInt("interface 2")
- delay = Param.Tick(0, "transmit delay of packets in us")
- speed = Param.Tick(100000000, "link speed in bits per second")
+ delay = Param.Latency('0us', "packet transmit delay")
+ speed = Param.NetworkBandwidth('100Mbps', "link speed")
dump = Param.EtherDump(NULL, "dump object")
simobj EtherBus(SimObject):
type = 'EtherBus'
- loopback = Param.Bool(True,
- "send packet back to the interface from which it came")
+ loopback = Param.Bool(True, "send packet back to the sending interface")
dump = Param.EtherDump(NULL, "dump object")
- speed = Param.UInt64(100000000, "bus speed in bits per second")
+ speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
simobj EtherTap(EtherInt):
type = 'EtherTap'
@@ -38,16 +37,16 @@ simobj EtherDev(DmaDevice):
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
- dma_read_delay = Param.Tick(0, "fixed delay for dma reads")
- dma_read_factor = Param.Tick(0, "multiplier for dma reads")
- dma_write_delay = Param.Tick(0, "fixed delay for dma writes")
- dma_write_factor = Param.Tick(0, "multiplier for dma writes")
+ dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
+ dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
+ dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
+ dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
rx_filter = Param.Bool(True, "Enable Receive Filter")
- rx_delay = Param.Tick(1000, "Receive Delay")
- tx_delay = Param.Tick(1000, "Transmit Delay")
+ rx_delay = Param.Latency('1us', "Receive Delay")
+ tx_delay = Param.Latency('1us', "Transmit Delay")
- intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
+ intr_delay = Param.Latency('0us', "Interrupt Delay")
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
tlaser = Param.Turbolaser(parent.any, "Turbolaser")
@@ -57,21 +56,23 @@ simobj NSGigE(PciDevice):
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
+ cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
+
dma_data_free = Param.Bool(False, "DMA of Data is free")
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
- dma_read_delay = Param.Tick(0, "fixed delay for dma reads")
- dma_read_factor = Param.Tick(0, "multiplier for dma reads")
- dma_write_delay = Param.Tick(0, "fixed delay for dma writes")
- dma_write_factor = Param.Tick(0, "multiplier for dma writes")
+ dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
+ dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
+ dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
+ dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
rx_filter = Param.Bool(True, "Enable Receive Filter")
- rx_delay = Param.Tick(1000, "Receive Delay")
- tx_delay = Param.Tick(1000, "Transmit Delay")
+ rx_delay = Param.Latency('1us', "Receive Delay")
+ tx_delay = Param.Latency('1us', "Transmit Delay")
rx_fifo_size = Param.MemorySize('128kB', "max size in bytes of rxFifo")
tx_fifo_size = Param.MemorySize('128kB', "max size in bytes of txFifo")
- intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
+ intr_delay = Param.Latency('0us', "Interrupt Delay in microseconds")
payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
physmem = Param.PhysicalMemory(parent.any, "Physical Memory")
diff --git a/python/m5/objects/Ide.mpy b/python/m5/objects/Ide.mpy
index 786109efa..02b1d9567 100644
--- a/python/m5/objects/Ide.mpy
+++ b/python/m5/objects/Ide.mpy
@@ -4,7 +4,7 @@ class IdeID(Enum): vals = ['master', 'slave']
simobj IdeDisk(SimObject):
type = 'IdeDisk'
- delay = Param.Tick(1, "Fixed disk delay in microseconds")
+ delay = Param.Latency('1us', "Fixed disk delay in microseconds")
driveID = Param.IdeID('master', "Drive ID")
image = Param.DiskImage("Disk image")
physmem = Param.PhysicalMemory(parent.any, "Physical memory")
diff --git a/python/m5/objects/Platform.mpy b/python/m5/objects/Platform.mpy
index a71ab3b77..166f3f4a1 100644
--- a/python/m5/objects/Platform.mpy
+++ b/python/m5/objects/Platform.mpy
@@ -1,5 +1,4 @@
simobj Platform(SimObject):
type = 'Platform'
abstract = True
- interrupt_frequency = Param.Tick(1200, "frequency of interrupts")
intrctrl = Param.IntrControl(parent.any, "interrupt controller")
diff --git a/python/m5/objects/Tsunami.mpy b/python/m5/objects/Tsunami.mpy
index a8471cee2..c17eae121 100644
--- a/python/m5/objects/Tsunami.mpy
+++ b/python/m5/objects/Tsunami.mpy
@@ -5,7 +5,6 @@ simobj Tsunami(Platform):
type = 'Tsunami'
pciconfig = Param.PciConfigAll("PCI configuration")
system = Param.BaseSystem(parent.any, "system")
- interrupt_frequency = Param.Int(1024, "frequency of interrupts")
simobj TsunamiCChip(FooPioDevice):
type = 'TsunamiCChip'
@@ -19,6 +18,7 @@ simobj TsunamiIO(FooPioDevice):
time = Param.UInt64(1136073600,
"System time to use (0 for actual time, default is 1/1/06)")
tsunami = Param.Tsunami(parent.any, "Tsunami")
+ frequency = Param.Frequency('1024Hz', "frequency of interrupts")
simobj TsunamiPChip(FooPioDevice):
type = 'TsunamiPChip'
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-08 23:05:04 +0000