diff options
Diffstat (limited to 'python/m5/objects')
27 files changed, 0 insertions, 620 deletions
diff --git a/python/m5/objects/AlphaConsole.py b/python/m5/objects/AlphaConsole.py deleted file mode 100644 index 68e6089ab..000000000 --- a/python/m5/objects/AlphaConsole.py +++ /dev/null @@ -1,9 +0,0 @@ -from m5 import * -from Device import BasicPioDevice - -class AlphaConsole(BasicPioDevice): - type = 'AlphaConsole' - cpu = Param.BaseCPU(Parent.any, "Processor") - disk = Param.SimpleDisk("Simple Disk") - sim_console = Param.SimConsole(Parent.any, "The Simulator Console") - system = Param.AlphaSystem(Parent.any, "system object") diff --git a/python/m5/objects/AlphaFullCPU.py b/python/m5/objects/AlphaFullCPU.py deleted file mode 100644 index 48989d057..000000000 --- a/python/m5/objects/AlphaFullCPU.py +++ /dev/null @@ -1,80 +0,0 @@ -from m5 import * -from BaseCPU import BaseCPU - -class DerivAlphaFullCPU(BaseCPU): - type = 'DerivAlphaFullCPU' - - numThreads = Param.Unsigned("number of HW thread contexts") - - if not build_env['FULL_SYSTEM']: - mem = Param.FunctionalMemory(NULL, "memory") - - decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") - renameToFetchDelay = Param.Unsigned("Rename to fetch delay") - iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch " - "delay") - commitToFetchDelay = Param.Unsigned("Commit to fetch delay") - fetchWidth = Param.Unsigned("Fetch width") - - renameToDecodeDelay = Param.Unsigned("Rename to decode delay") - iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode " - "delay") - commitToDecodeDelay = Param.Unsigned("Commit to decode delay") - fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay") - decodeWidth = Param.Unsigned("Decode width") - - iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename " - "delay") - commitToRenameDelay = Param.Unsigned("Commit to rename delay") - decodeToRenameDelay = Param.Unsigned("Decode to rename delay") - renameWidth = Param.Unsigned("Rename width") - - commitToIEWDelay = Param.Unsigned("Commit to " - "Issue/Execute/Writeback delay") - renameToIEWDelay = Param.Unsigned("Rename to " - "Issue/Execute/Writeback delay") - issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal " - "to the IEW stage)") - issueWidth = Param.Unsigned("Issue width") - executeWidth = Param.Unsigned("Execute width") - executeIntWidth = Param.Unsigned("Integer execute width") - executeFloatWidth = Param.Unsigned("Floating point execute width") - executeBranchWidth = Param.Unsigned("Branch execute width") - executeMemoryWidth = Param.Unsigned("Memory execute width") - - iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit " - "delay") - renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay") - commitWidth = Param.Unsigned("Commit width") - squashWidth = Param.Unsigned("Squash width") - - local_predictor_size = Param.Unsigned("Size of local predictor") - local_ctr_bits = Param.Unsigned("Bits per counter") - local_history_table_size = Param.Unsigned("Size of local history table") - local_history_bits = Param.Unsigned("Bits for the local history") - global_predictor_size = Param.Unsigned("Size of global predictor") - global_ctr_bits = Param.Unsigned("Bits per counter") - global_history_bits = Param.Unsigned("Bits of history") - choice_predictor_size = Param.Unsigned("Size of choice predictor") - choice_ctr_bits = Param.Unsigned("Bits of choice counters") - - BTBEntries = Param.Unsigned("Number of BTB entries") - BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits") - - RASSize = Param.Unsigned("RAS size") - - LQEntries = Param.Unsigned("Number of load queue entries") - SQEntries = Param.Unsigned("Number of store queue entries") - LFSTSize = Param.Unsigned("Last fetched store table size") - SSITSize = Param.Unsigned("Store set ID table size") - - numPhysIntRegs = Param.Unsigned("Number of physical integer registers") - numPhysFloatRegs = Param.Unsigned("Number of physical floating point " - "registers") - numIQEntries = Param.Unsigned("Number of instruction queue entries") - numROBEntries = Param.Unsigned("Number of reorder buffer entries") - - instShiftAmt = Param.Unsigned("Number of bits to shift instructions by") - - function_trace = Param.Bool(False, "Enable function trace") - function_trace_start = Param.Tick(0, "Cycle to start function trace") diff --git a/python/m5/objects/AlphaTLB.py b/python/m5/objects/AlphaTLB.py deleted file mode 100644 index 5edf8e13d..000000000 --- a/python/m5/objects/AlphaTLB.py +++ /dev/null @@ -1,13 +0,0 @@ -from m5 import * -class AlphaTLB(SimObject): - type = 'AlphaTLB' - abstract = True - size = Param.Int("TLB size") - -class AlphaDTB(AlphaTLB): - type = 'AlphaDTB' - size = 64 - -class AlphaITB(AlphaTLB): - type = 'AlphaITB' - size = 48 diff --git a/python/m5/objects/BadDevice.py b/python/m5/objects/BadDevice.py deleted file mode 100644 index 9cb9a8f03..000000000 --- a/python/m5/objects/BadDevice.py +++ /dev/null @@ -1,6 +0,0 @@ -from m5 import * -from Device import BasicPioDevice - -class BadDevice(BasicPioDevice): - type = 'BadDevice' - devicename = Param.String("Name of device to error on") diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py deleted file mode 100644 index 49cb2a8f3..000000000 --- a/python/m5/objects/BaseCPU.py +++ /dev/null @@ -1,27 +0,0 @@ -from m5 import * -class BaseCPU(SimObject): - type = 'BaseCPU' - abstract = True - mem = Param.MemObject("memory") - - if build_env['FULL_SYSTEM']: - dtb = Param.AlphaDTB("Data TLB") - itb = Param.AlphaITB("Instruction TLB") - system = Param.System(Parent.any, "system object") - cpu_id = Param.Int(-1, "CPU identifier") - else: - workload = VectorParam.Process("processes to run") - - max_insts_all_threads = Param.Counter(0, - "terminate when all threads have reached this inst count") - max_insts_any_thread = Param.Counter(0, - "terminate when any thread reaches this inst count") - max_loads_all_threads = Param.Counter(0, - "terminate when all threads have reached this load count") - max_loads_any_thread = Param.Counter(0, - "terminate when any thread reaches this load count") - - defer_registration = Param.Bool(False, - "defer registration with system (for sampling)") - - clock = Param.Clock(Parent.clock, "clock speed") diff --git a/python/m5/objects/BaseCache.py b/python/m5/objects/BaseCache.py deleted file mode 100644 index 79d21572a..000000000 --- a/python/m5/objects/BaseCache.py +++ /dev/null @@ -1,65 +0,0 @@ -from m5 import * -from BaseMem import BaseMem - -class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb'] - -class BaseCache(BaseMem): - type = 'BaseCache' - adaptive_compression = Param.Bool(False, - "Use an adaptive compression scheme") - assoc = Param.Int("associativity") - block_size = Param.Int("block size in bytes") - compressed_bus = Param.Bool(False, - "This cache connects to a compressed memory") - compression_latency = Param.Latency('0ns', - "Latency in cycles of compression algorithm") - do_copy = Param.Bool(False, "perform fast copies in the cache") - hash_delay = Param.Int(1, "time in cycles of hash access") - in_bus = Param.Bus(NULL, "incoming bus object") - lifo = Param.Bool(False, - "whether this NIC partition should use LIFO repl. policy") - max_miss_count = Param.Counter(0, - "number of misses to handle before calling exit") - mem_trace = Param.MemTraceWriter(NULL, - "memory trace writer to record accesses") - mshrs = Param.Int("number of MSHRs (max outstanding requests)") - out_bus = Param.Bus("outgoing bus object") - prioritizeRequests = Param.Bool(False, - "always service demand misses first") - protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use") - repl = Param.Repl(NULL, "replacement policy") - size = Param.MemorySize("capacity in bytes") - split = Param.Bool(False, "whether or not this cache is split") - split_size = Param.Int(0, - "How many ways of the cache belong to CPU/LRU partition") - store_compressed = Param.Bool(False, - "Store compressed data in the cache") - subblock_size = Param.Int(0, - "Size of subblock in IIC used for compression") - tgts_per_mshr = Param.Int("max number of accesses per MSHR") - trace_addr = Param.Addr(0, "address to trace") - two_queue = Param.Bool(False, - "whether the lifo should have two queue replacement") - write_buffers = Param.Int(8, "number of write buffers") - prefetch_miss = Param.Bool(False, - "wheter you are using the hardware prefetcher from Miss stream") - prefetch_access = Param.Bool(False, - "wheter you are using the hardware prefetcher from Access stream") - prefetcher_size = Param.Int(100, - "Number of entries in the harware prefetch queue") - prefetch_past_page = Param.Bool(False, - "Allow prefetches to cross virtual page boundaries") - prefetch_serial_squash = Param.Bool(False, - "Squash prefetches with a later time on a subsequent miss") - prefetch_degree = Param.Int(1, - "Degree of the prefetch depth") - prefetch_latency = Param.Tick(10, - "Latency of the prefetcher") - prefetch_policy = Param.Prefetch('none', - "Type of prefetcher to use") - prefetch_cache_check_push = Param.Bool(True, - "Check if in cash on push or pop of prefetch queue") - prefetch_use_cpu_id = Param.Bool(True, - "Use the CPU ID to seperate calculations of prefetches") - prefetch_data_accesses_only = Param.Bool(False, - "Only prefetch on data not on instruction accesses") diff --git a/python/m5/objects/Bridge.py b/python/m5/objects/Bridge.py deleted file mode 100644 index ada715ce9..000000000 --- a/python/m5/objects/Bridge.py +++ /dev/null @@ -1,9 +0,0 @@ -from m5 import * -from MemObject import MemObject - -class Bridge(MemObject): - type = 'Bridge' - queue_size_a = Param.Int(16, "The number of requests to buffer") - queue_size_b = Param.Int(16, "The number of requests to buffer") - delay = Param.Latency('0ns', "The latency of this bridge") - write_ack = Param.Bool(False, "Should this bridge ack writes") diff --git a/python/m5/objects/Bus.py b/python/m5/objects/Bus.py deleted file mode 100644 index 8c5397281..000000000 --- a/python/m5/objects/Bus.py +++ /dev/null @@ -1,6 +0,0 @@ -from m5 import * -from MemObject import MemObject - -class Bus(MemObject): - type = 'Bus' - bus_id = Param.Int(0, "blah") diff --git a/python/m5/objects/CoherenceProtocol.py b/python/m5/objects/CoherenceProtocol.py deleted file mode 100644 index 7013000d6..000000000 --- a/python/m5/objects/CoherenceProtocol.py +++ /dev/null @@ -1,7 +0,0 @@ -from m5 import * -class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi'] - -class CoherenceProtocol(SimObject): - type = 'CoherenceProtocol' - do_upgrades = Param.Bool(True, "use upgrade transactions?") - protocol = Param.Coherence("name of coherence protocol") diff --git a/python/m5/objects/Device.py b/python/m5/objects/Device.py deleted file mode 100644 index 2a71bbc65..000000000 --- a/python/m5/objects/Device.py +++ /dev/null @@ -1,18 +0,0 @@ -from m5 import * -from MemObject import MemObject - -class PioDevice(MemObject): - type = 'PioDevice' - abstract = True - platform = Param.Platform(Parent.any, "Platform this device is part of") - system = Param.System(Parent.any, "System this device is part of") - -class BasicPioDevice(PioDevice): - type = 'BasicPioDevice' - abstract = True - pio_addr = Param.Addr("Device Address") - pio_latency = Param.Tick(1, "Programmed IO latency in simticks") - -class DmaDevice(PioDevice): - type = 'DmaDevice' - abstract = True diff --git a/python/m5/objects/DiskImage.py b/python/m5/objects/DiskImage.py deleted file mode 100644 index 0d55e9329..000000000 --- a/python/m5/objects/DiskImage.py +++ /dev/null @@ -1,15 +0,0 @@ -from m5 import * -class DiskImage(SimObject): - type = 'DiskImage' - abstract = True - image_file = Param.String("disk image file") - read_only = Param.Bool(False, "read only image") - -class RawDiskImage(DiskImage): - type = 'RawDiskImage' - -class CowDiskImage(DiskImage): - type = 'CowDiskImage' - child = Param.DiskImage("child image") - table_size = Param.Int(65536, "initial table size") - image_file = '' diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py deleted file mode 100644 index 4286c71c8..000000000 --- a/python/m5/objects/Ethernet.py +++ /dev/null @@ -1,115 +0,0 @@ -from m5 import * -from Device import DmaDevice -from Pci import PciDevice - -class EtherInt(SimObject): - type = 'EtherInt' - abstract = True - peer = Param.EtherInt(NULL, "peer interface") - -class EtherLink(SimObject): - type = 'EtherLink' - int1 = Param.EtherInt("interface 1") - int2 = Param.EtherInt("interface 2") - delay = Param.Latency('0us', "packet transmit delay") - delay_var = Param.Latency('0ns', "packet transmit delay variability") - speed = Param.NetworkBandwidth('1Gbps', "link speed") - dump = Param.EtherDump(NULL, "dump object") - -class EtherBus(SimObject): - type = 'EtherBus' - loopback = Param.Bool(True, "send packet back to the sending interface") - dump = Param.EtherDump(NULL, "dump object") - speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second") - -class EtherTap(EtherInt): - type = 'EtherTap' - bufsz = Param.Int(10000, "tap buffer size") - dump = Param.EtherDump(NULL, "dump object") - port = Param.UInt16(3500, "tap port") - -class EtherDump(SimObject): - type = 'EtherDump' - file = Param.String("dump file") - maxlen = Param.Int(96, "max portion of packet data to dump") - -if build_env['ALPHA_TLASER']: - - class EtherDev(DmaDevice): - type = 'EtherDev' - hardware_address = Param.EthernetAddr(NextEthernetAddr, - "Ethernet Hardware Address") - - dma_data_free = Param.Bool(False, "DMA of Data is free") - dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") - dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") - dma_read_factor = Param.Latency('0us', "multiplier for dma reads") - dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") - dma_write_factor = Param.Latency('0us', "multiplier for dma writes") - dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") - - rx_filter = Param.Bool(True, "Enable Receive Filter") - rx_delay = Param.Latency('1us', "Receive Delay") - tx_delay = Param.Latency('1us', "Transmit Delay") - - intr_delay = Param.Latency('0us', "Interrupt Delay") - payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") - physmem = Param.PhysicalMemory(Parent.any, "Physical Memory") - tlaser = Param.Turbolaser(Parent.any, "Turbolaser") - - class EtherDevInt(EtherInt): - type = 'EtherDevInt' - device = Param.EtherDev("Ethernet device of this interface") - -class EtherDevBase(PciDevice): - hardware_address = Param.EthernetAddr(NextEthernetAddr, - "Ethernet Hardware Address") - - clock = Param.Clock('0ns', "State machine processor frequency") - - dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") - dma_read_factor = Param.Latency('0us', "multiplier for dma reads") - dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") - dma_write_factor = Param.Latency('0us', "multiplier for dma writes") - - rx_delay = Param.Latency('1us', "Receive Delay") - tx_delay = Param.Latency('1us', "Transmit Delay") - rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo") - tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo") - - rx_filter = Param.Bool(True, "Enable Receive Filter") - intr_delay = Param.Latency('10us', "Interrupt propagation delay") - rx_thread = Param.Bool(False, "dedicated kernel thread for transmit") - tx_thread = Param.Bool(False, "dedicated kernel threads for receive") - rss = Param.Bool(False, "Receive Side Scaling") - -class NSGigE(EtherDevBase): - type = 'NSGigE' - - dma_data_free = Param.Bool(False, "DMA of Data is free") - dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") - dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") - - -class NSGigEInt(EtherInt): - type = 'NSGigEInt' - device = Param.NSGigE("Ethernet device of this interface") - -class Sinic(EtherDevBase): - type = 'Sinic' - - rx_max_copy = Param.MemorySize('1514B', "rx max copy") - tx_max_copy = Param.MemorySize('16kB', "tx max copy") - rx_max_intr = Param.UInt32(10, "max rx packets per interrupt") - rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold") - rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold") - tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold") - tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold") - virtual_count = Param.UInt32(1, "Virtualized SINIC") - zero_copy = Param.Bool(False, "Zero copy receive") - delay_copy = Param.Bool(False, "Delayed copy transmit") - virtual_addr = Param.Bool(False, "Virtual addressing") - -class SinicInt(EtherInt): - type = 'SinicInt' - device = Param.Sinic("Ethernet device of this interface") diff --git a/python/m5/objects/Ide.py b/python/m5/objects/Ide.py deleted file mode 100644 index 2403e6d36..000000000 --- a/python/m5/objects/Ide.py +++ /dev/null @@ -1,14 +0,0 @@ -from m5 import * -from Pci import PciDevice - -class IdeID(Enum): vals = ['master', 'slave'] - -class IdeDisk(SimObject): - type = 'IdeDisk' - delay = Param.Latency('1us', "Fixed disk delay in microseconds") - driveID = Param.IdeID('master', "Drive ID") - image = Param.DiskImage("Disk image") - -class IdeController(PciDevice): - type = 'IdeController' - disks = VectorParam.IdeDisk("IDE disks attached to this controller") diff --git a/python/m5/objects/IntrControl.py b/python/m5/objects/IntrControl.py deleted file mode 100644 index 66c82c182..000000000 --- a/python/m5/objects/IntrControl.py +++ /dev/null @@ -1,4 +0,0 @@ -from m5 import * -class IntrControl(SimObject): - type = 'IntrControl' - cpu = Param.BaseCPU(Parent.any, "the cpu") diff --git a/python/m5/objects/MemObject.py b/python/m5/objects/MemObject.py deleted file mode 100644 index 4d68243e6..000000000 --- a/python/m5/objects/MemObject.py +++ /dev/null @@ -1,5 +0,0 @@ -from m5 import * - -class MemObject(SimObject): - type = 'MemObject' - abstract = True diff --git a/python/m5/objects/MemTest.py b/python/m5/objects/MemTest.py deleted file mode 100644 index 34299faf0..000000000 --- a/python/m5/objects/MemTest.py +++ /dev/null @@ -1,19 +0,0 @@ -from m5 import * -class MemTest(SimObject): - type = 'MemTest' - cache = Param.BaseCache("L1 cache") - check_mem = Param.FunctionalMemory("check memory") - main_mem = Param.FunctionalMemory("hierarchical memory") - max_loads = Param.Counter("number of loads to execute") - memory_size = Param.Int(65536, "memory size") - percent_copies = Param.Percent(0, "target copy percentage") - percent_dest_unaligned = Param.Percent(50, - "percent of copy dest address that are unaligned") - percent_reads = Param.Percent(65, "target read percentage") - percent_source_unaligned = Param.Percent(50, - "percent of copy source address that are unaligned") - percent_uncacheable = Param.Percent(10, - "target uncacheable percentage") - progress_interval = Param.Counter(1000000, - "progress report interval (in accesses)") - trace_addr = Param.Addr(0, "address to trace") diff --git a/python/m5/objects/Pci.py b/python/m5/objects/Pci.py deleted file mode 100644 index 85cefcd44..000000000 --- a/python/m5/objects/Pci.py +++ /dev/null @@ -1,55 +0,0 @@ -from m5 import * -from Device import BasicPioDevice, DmaDevice - -class PciConfigData(SimObject): - type = 'PciConfigData' - VendorID = Param.UInt16("Vendor ID") - DeviceID = Param.UInt16("Device ID") - Command = Param.UInt16(0, "Command") - Status = Param.UInt16(0, "Status") - Revision = Param.UInt8(0, "Device") - ProgIF = Param.UInt8(0, "Programming Interface") - SubClassCode = Param.UInt8(0, "Sub-Class Code") - ClassCode = Param.UInt8(0, "Class Code") - CacheLineSize = Param.UInt8(0, "System Cacheline Size") - LatencyTimer = Param.UInt8(0, "PCI Latency Timer") - HeaderType = Param.UInt8(0, "PCI Header Type") - BIST = Param.UInt8(0, "Built In Self Test") - - BAR0 = Param.UInt32(0x00, "Base Address Register 0") - BAR1 = Param.UInt32(0x00, "Base Address Register 1") - BAR2 = Param.UInt32(0x00, "Base Address Register 2") - BAR3 = Param.UInt32(0x00, "Base Address Register 3") - BAR4 = Param.UInt32(0x00, "Base Address Register 4") - BAR5 = Param.UInt32(0x00, "Base Address Register 5") - BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size") - BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size") - BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size") - BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size") - BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size") - BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size") - - CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure") - SubsystemID = Param.UInt16(0x00, "Subsystem ID") - SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID") - ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address") - InterruptLine = Param.UInt8(0x00, "Interrupt Line") - InterruptPin = Param.UInt8(0x00, "Interrupt Pin") - MaximumLatency = Param.UInt8(0x00, "Maximum Latency") - MinimumGrant = Param.UInt8(0x00, "Minimum Grant") - -class PciConfigAll(BasicPioDevice): - type = 'PciConfigAll' - -class PciDevice(DmaDevice): - type = 'PciDevice' - abstract = True - pci_bus = Param.Int("PCI bus") - pci_dev = Param.Int("PCI device number") - pci_func = Param.Int("PCI function code") - pio_latency = Param.Tick(1, "Programmed IO latency in simticks") - configdata = Param.PciConfigData(Parent.any, "PCI Config data") - configspace = Param.PciConfigAll(Parent.any, "PCI Configspace") - -class PciFake(PciDevice): - type = 'PciFake' diff --git a/python/m5/objects/PhysicalMemory.py b/python/m5/objects/PhysicalMemory.py deleted file mode 100644 index c59910093..000000000 --- a/python/m5/objects/PhysicalMemory.py +++ /dev/null @@ -1,8 +0,0 @@ -from m5 import * -from MemObject import * - -class PhysicalMemory(MemObject): - type = 'PhysicalMemory' - range = Param.AddrRange("Device Address") - file = Param.String('', "memory mapped file") - latency = Param.Latency(Parent.clock, "latency of an access") diff --git a/python/m5/objects/Platform.py b/python/m5/objects/Platform.py deleted file mode 100644 index 4da0ffab4..000000000 --- a/python/m5/objects/Platform.py +++ /dev/null @@ -1,5 +0,0 @@ -from m5 import * -class Platform(SimObject): - type = 'Platform' - abstract = True - intrctrl = Param.IntrControl(Parent.any, "interrupt controller") diff --git a/python/m5/objects/Process.py b/python/m5/objects/Process.py deleted file mode 100644 index 60b00229e..000000000 --- a/python/m5/objects/Process.py +++ /dev/null @@ -1,27 +0,0 @@ -from m5 import * -class Process(SimObject): - type = 'Process' - abstract = True - output = Param.String('cout', 'filename for stdout/stderr') - system = Param.System(Parent.any, "system process will run on") - -class LiveProcess(Process): - type = 'LiveProcess' - executable = Param.String('', "executable (overrides cmd[0] if set)") - cmd = VectorParam.String("command line (executable plus arguments)") - env = VectorParam.String('', "environment settings") - input = Param.String('cin', "filename for stdin") - -class AlphaLiveProcess(LiveProcess): - type = 'AlphaLiveProcess' - -class SparcLiveProcess(LiveProcess): - type = 'SparcLiveProcess' - -class MipsLiveProcess(LiveProcess): - type = 'MipsLiveProcess' - -class EioProcess(Process): - type = 'EioProcess' - chkpt = Param.String('', "EIO checkpoint file name (optional)") - file = Param.String("EIO trace file name") diff --git a/python/m5/objects/Repl.py b/python/m5/objects/Repl.py deleted file mode 100644 index afd256082..000000000 --- a/python/m5/objects/Repl.py +++ /dev/null @@ -1,10 +0,0 @@ -from m5 import * -class Repl(SimObject): - type = 'Repl' - abstract = True - -class GenRepl(Repl): - type = 'GenRepl' - fresh_res = Param.Int("associativity") - num_pools = Param.Int("capacity in bytes") - pool_res = Param.Int("block size in bytes") diff --git a/python/m5/objects/Root.py b/python/m5/objects/Root.py deleted file mode 100644 index 205a93c76..000000000 --- a/python/m5/objects/Root.py +++ /dev/null @@ -1,23 +0,0 @@ -from m5 import * -from Serialize import Serialize -from Statistics import Statistics -from Trace import Trace -from ExeTrace import ExecutionTrace -from Debug import Debug - -class Root(SimObject): - type = 'Root' - clock = Param.RootClock('200MHz', "tick frequency") - max_tick = Param.Tick('0', "maximum simulation ticks (0 = infinite)") - progress_interval = Param.Tick('0', - "print a progress message every n ticks (0 = never)") - output_file = Param.String('cout', "file to dump simulator output to") - checkpoint = Param.String('', "checkpoint file to load") -# stats = Param.Statistics(Statistics(), "statistics object") -# trace = Param.Trace(Trace(), "trace object") -# serialize = Param.Serialize(Serialize(), "checkpoint generation options") - stats = Statistics() - trace = Trace() - exetrace = ExecutionTrace() - serialize = Serialize() - debug = Debug() diff --git a/python/m5/objects/SimConsole.py b/python/m5/objects/SimConsole.py deleted file mode 100644 index df3061908..000000000 --- a/python/m5/objects/SimConsole.py +++ /dev/null @@ -1,12 +0,0 @@ -from m5 import * -class ConsoleListener(SimObject): - type = 'ConsoleListener' - port = Param.TcpPort(3456, "listen port") - -class SimConsole(SimObject): - type = 'SimConsole' - append_name = Param.Bool(True, "append name() to filename") - intr_control = Param.IntrControl(Parent.any, "interrupt controller") - listener = Param.ConsoleListener("console listener") - number = Param.Int(0, "console number") - output = Param.String('console', "file to dump output to") diff --git a/python/m5/objects/SimpleDisk.py b/python/m5/objects/SimpleDisk.py deleted file mode 100644 index e34155ace..000000000 --- a/python/m5/objects/SimpleDisk.py +++ /dev/null @@ -1,5 +0,0 @@ -from m5 import * -class SimpleDisk(SimObject): - type = 'SimpleDisk' - disk = Param.DiskImage("Disk Image") - system = Param.System(Parent.any, "Sysetm Pointer") diff --git a/python/m5/objects/System.py b/python/m5/objects/System.py deleted file mode 100644 index 622b5a870..000000000 --- a/python/m5/objects/System.py +++ /dev/null @@ -1,21 +0,0 @@ -from m5 import * - -class System(SimObject): - type = 'System' - physmem = Param.PhysicalMemory(Parent.any, "phsyical memory") - if build_env['FULL_SYSTEM']: - boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency, - "boot processor frequency") - init_param = Param.UInt64(0, "numerical value to pass into simulator") - bin = Param.Bool(False, "is this system binned") - binned_fns = VectorParam.String([], "functions broken down and binned") - boot_osflags = Param.String("a", "boot flags to pass to the kernel") - kernel = Param.String("file that contains the kernel code") - readfile = Param.String("", "file to read startup script from") - -class AlphaSystem(System): - type = 'AlphaSystem' - console = Param.String("file that contains the console code") - pal = Param.String("file that contains palcode") - system_type = Param.UInt64("Type of system we are emulating") - system_rev = Param.UInt64("Revision of system we are emulating") diff --git a/python/m5/objects/Tsunami.py b/python/m5/objects/Tsunami.py deleted file mode 100644 index 27ea0bce8..000000000 --- a/python/m5/objects/Tsunami.py +++ /dev/null @@ -1,27 +0,0 @@ -from m5 import * -from Device import BasicPioDevice -from Platform import Platform - -class Tsunami(Platform): - type = 'Tsunami' -# pciconfig = Param.PciConfigAll("PCI configuration") - system = Param.System(Parent.any, "system") - -class TsunamiCChip(BasicPioDevice): - type = 'TsunamiCChip' - tsunami = Param.Tsunami(Parent.any, "Tsunami") - -class IsaFake(BasicPioDevice): - type = 'IsaFake' - pio_size = Param.Addr(0x8, "Size of address range") - -class TsunamiIO(BasicPioDevice): - type = 'TsunamiIO' - time = Param.UInt64(1136073600, - "System time to use (0 for actual time, default is 1/1/06)") - tsunami = Param.Tsunami(Parent.any, "Tsunami") - frequency = Param.Frequency('1024Hz', "frequency of interrupts") - -class TsunamiPChip(BasicPioDevice): - type = 'TsunamiPChip' - tsunami = Param.Tsunami(Parent.any, "Tsunami") diff --git a/python/m5/objects/Uart.py b/python/m5/objects/Uart.py deleted file mode 100644 index 54754aeb9..000000000 --- a/python/m5/objects/Uart.py +++ /dev/null @@ -1,15 +0,0 @@ -from m5 import * -from Device import BasicPioDevice - -class Uart(BasicPioDevice): - type = 'Uart' - abstract = True - sim_console = Param.SimConsole(Parent.any, "The console") - -class Uart8250(Uart): - type = 'Uart8250' - -if build_env['ALPHA_TLASER']: - class Uart8530(Uart): - type = 'Uart8530' - |