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-rw-r--r--python/m5/objects/Bus.mpy2
-rw-r--r--python/m5/objects/Root.mpy2
2 files changed, 2 insertions, 2 deletions
diff --git a/python/m5/objects/Bus.mpy b/python/m5/objects/Bus.mpy
index 330a2c82b..aa12f757a 100644
--- a/python/m5/objects/Bus.mpy
+++ b/python/m5/objects/Bus.mpy
@@ -2,5 +2,5 @@ from BaseHier import BaseHier
simobj Bus(BaseHier):
type = 'Bus'
- clock_ratio = Param.Frequency("ratio of CPU to bus frequency")
+ clock_ratio = Param.ClockPeriod("ratio of CPU to bus frequency")
width = Param.Int("bus width in bytes")
diff --git a/python/m5/objects/Root.mpy b/python/m5/objects/Root.mpy
index 0e531054b..c535bd2dc 100644
--- a/python/m5/objects/Root.mpy
+++ b/python/m5/objects/Root.mpy
@@ -5,7 +5,7 @@ from Trace import Trace
simobj Root(SimObject):
type = 'Root'
- frequency = Param.Tick(200000000, "tick frequency")
+ frequency = Param.RootFrequency('200MHz', "tick frequency")
output_file = Param.String('cout', "file to dump simulator output to")
full_system = Param.Bool("Full system simulation?")
hier = HierParams(do_data = False, do_events = True)