6 files changed, 7 insertions, 7 deletions
diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py
index d4fa13d3b..0dc436434 100644
--- a/python/m5/objects/BaseCPU.py
+++ b/python/m5/objects/BaseCPU.py
@@ -25,4 +25,4 @@ class BaseCPU(SimObject):
     defer_registration = Param.Bool(False,
         "defer registration with system (for sampling)")
 
-    cycle_time = Param.Latency(Parent.frequency.latency, "clock speed")
+    clock = Param.Clock(Parent.clock, "clock speed")
diff --git a/python/m5/objects/BaseCache.py b/python/m5/objects/BaseCache.py
index d311969fa..79d21572a 100644
--- a/python/m5/objects/BaseCache.py
+++ b/python/m5/objects/BaseCache.py
@@ -11,7 +11,7 @@ class BaseCache(BaseMem):
     block_size = Param.Int("block size in bytes")
     compressed_bus = Param.Bool(False,
         "This cache connects to a compressed memory")
-    compression_latency = Param.Latency(0,
+    compression_latency = Param.Latency('0ns',
         "Latency in cycles of compression algorithm")
     do_copy = Param.Bool(False, "perform fast copies in the cache")
     hash_delay = Param.Int(1, "time in cycles of hash access")
diff --git a/python/m5/objects/BaseSystem.py b/python/m5/objects/BaseSystem.py
index 48c70e44f..457eadb36 100644
--- a/python/m5/objects/BaseSystem.py
+++ b/python/m5/objects/BaseSystem.py
@@ -2,7 +2,7 @@ from m5 import *
 class BaseSystem(SimObject):
     type = 'BaseSystem'
     abstract = True
-    boot_cpu_frequency = Param.Frequency(Self.cpu[0].cycle_time.frequency,
+    boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
                                          "boot processor frequency")
     memctrl = Param.MemoryController(Parent.any, "memory controller")
     physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
diff --git a/python/m5/objects/Bus.py b/python/m5/objects/Bus.py
index 1ed87d2e7..26509d7d2 100644
--- a/python/m5/objects/Bus.py
+++ b/python/m5/objects/Bus.py
@@ -3,5 +3,5 @@ from BaseHier import BaseHier
 
 class Bus(BaseHier):
     type = 'Bus'
-    clock_ratio = Param.Frequency("ratio of CPU to bus frequency")
+    clock = Param.Clock("bus frequency")
     width = Param.Int("bus width in bytes")
diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py
index 69dec1528..c89505477 100644
--- a/python/m5/objects/Ethernet.py
+++ b/python/m5/objects/Ethernet.py
@@ -58,7 +58,7 @@ class NSGigE(PciDevice):
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
 
-    cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
+    clock = Param.Clock('100MHz', "State machine processor frequency")
 
     dma_data_free = Param.Bool(False, "DMA of Data is free")
     dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
@@ -95,7 +95,7 @@ class Sinic(PciDevice):
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
 
-    cycle_time = Param.Frequency('100MHz', "State machine processor frequency")
+    clock = Param.Clock('100MHz', "State machine processor frequency")
 
     dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
     dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
diff --git a/python/m5/objects/Root.py b/python/m5/objects/Root.py
index 78d5388f0..79e3721fc 100644
--- a/python/m5/objects/Root.py
+++ b/python/m5/objects/Root.py
@@ -6,7 +6,7 @@ from Trace import Trace
 
 class Root(SimObject):
     type = 'Root'
-    frequency = Param.RootFrequency('200MHz', "tick frequency")
+    clock = Param.RootClock('200MHz', "tick frequency")
     output_file = Param.String('cout', "file to dump simulator output to")
     checkpoint = Param.String('', "checkpoint file to load")
 #    hier = Param.HierParams(HierParams(do_data = False, do_events = True),