6 files changed, 11 insertions, 11 deletions
diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py
index a90203729..07cb850f1 100644
--- a/python/m5/objects/BaseCPU.py
+++ b/python/m5/objects/BaseCPU.py
@@ -2,16 +2,14 @@ from m5 import *
 class BaseCPU(SimObject):
     type = 'BaseCPU'
     abstract = True
-    icache = Param.BaseMem(NULL, "L1 instruction cache object")
-    dcache = Param.BaseMem(NULL, "L1 data cache object")
 
     if build_env['FULL_SYSTEM']:
         dtb = Param.AlphaDTB("Data TLB")
         itb = Param.AlphaITB("Instruction TLB")
-        mem = Param.FunctionalMemory("memory")
         system = Param.System(Parent.any, "system object")
         cpu_id = Param.Int(-1, "CPU identifier")
     else:
+        mem = Param.Memory(Parent.any, "memory")
         workload = VectorParam.Process("processes to run")
 
     max_insts_all_threads = Param.Counter(0,
diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py
index 6113e656f..22714e15c 100644
--- a/python/m5/objects/Ethernet.py
+++ b/python/m5/objects/Ethernet.py
@@ -69,7 +69,6 @@ class EtherDevBase(PciDevice):
 
     physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
 
-    hier = Param.HierParams(Parent.any, "Hierarchy global variables")
     payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
     dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
     dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
diff --git a/python/m5/objects/MemObject.py b/python/m5/objects/MemObject.py
new file mode 100644
index 000000000..4d68243e6
--- /dev/null
+++ b/python/m5/objects/MemObject.py
@@ -0,0 +1,5 @@
+from m5 import *
+
+class MemObject(SimObject):
+    type = 'MemObject'
+    abstract = True
diff --git a/python/m5/objects/PhysicalMemory.py b/python/m5/objects/PhysicalMemory.py
index f50937ee6..b0aba1a7d 100644
--- a/python/m5/objects/PhysicalMemory.py
+++ b/python/m5/objects/PhysicalMemory.py
@@ -1,8 +1,9 @@
 from m5 import *
-from FunctionalMemory import FunctionalMemory
+from Memory import Memory
 
-class PhysicalMemory(FunctionalMemory):
+class PhysicalMemory(Memory):
     type = 'PhysicalMemory'
     range = Param.AddrRange("Device Address")
     file = Param.String('', "memory mapped file")
-    mmu = Param.MemoryController(Parent.any, "Memory Controller")
+    if build_env['FULL_SYSTEM']:
+        mmu = Param.MemoryController(Parent.any, "Memory Controller")
diff --git a/python/m5/objects/Process.py b/python/m5/objects/Process.py
index b4ccc1bec..def70dbaa 100644
--- a/python/m5/objects/Process.py
+++ b/python/m5/objects/Process.py
@@ -3,6 +3,7 @@ class Process(SimObject):
     type = 'Process'
     abstract = True
     output = Param.String('cout', 'filename for stdout/stderr')
+    system = Param.System(Parent.any, "system process will run on")
 
 class LiveProcess(Process):
     type = 'LiveProcess'
diff --git a/python/m5/objects/Root.py b/python/m5/objects/Root.py
index 23b13fc67..f51516098 100644
--- a/python/m5/objects/Root.py
+++ b/python/m5/objects/Root.py
@@ -1,5 +1,4 @@
 from m5 import *
-from HierParams import HierParams
 from Serialize import Serialize
 from Statistics import Statistics
 from Trace import Trace
@@ -13,12 +12,9 @@ class Root(SimObject):
         "print a progress message every n ticks (0 = never)")
     output_file = Param.String('cout', "file to dump simulator output to")
     checkpoint = Param.String('', "checkpoint file to load")
-#    hier = Param.HierParams(HierParams(do_data = False, do_events = True),
-#                            "shared memory hierarchy parameters")
 #    stats = Param.Statistics(Statistics(), "statistics object")
 #    trace = Param.Trace(Trace(), "trace object")
 #    serialize = Param.Serialize(Serialize(), "checkpoint generation options")
-    hier = HierParams(do_data = False, do_events = True)
     stats = Statistics()
     trace = Trace()
     exetrace = ExecutionTrace()