diff options
Diffstat (limited to 'python/m5/objects')
24 files changed, 433 insertions, 0 deletions
diff --git a/python/m5/objects/AlphaConsole.mpy b/python/m5/objects/AlphaConsole.mpy new file mode 100644 index 000000000..79918a01e --- /dev/null +++ b/python/m5/objects/AlphaConsole.mpy @@ -0,0 +1,9 @@ +from Device import PioDevice + +simobj AlphaConsole(PioDevice): + type = 'AlphaConsole' + cpu = Param.BaseCPU(Super, "Processor") + disk = Param.SimpleDisk("Simple Disk") + num_cpus = Param.Int(1, "Number of CPUs") + sim_console = Param.SimConsole(Super, "The Simulator Console") + system = Param.BaseSystem(Super, "system object") diff --git a/python/m5/objects/AlphaTLB.mpy b/python/m5/objects/AlphaTLB.mpy new file mode 100644 index 000000000..8e7cd62cc --- /dev/null +++ b/python/m5/objects/AlphaTLB.mpy @@ -0,0 +1,12 @@ +simobj AlphaTLB(SimObject): + type = 'AlphaTLB' + abstract = True + size = Param.Int("TLB size") + +simobj AlphaDTB(AlphaTLB): + type = 'AlphaDTB' + size = 64 + +simobj AlphaITB(AlphaTLB): + type = 'AlphaITB' + size = 48 diff --git a/python/m5/objects/BadDevice.mpy b/python/m5/objects/BadDevice.mpy new file mode 100644 index 000000000..35a12e0bf --- /dev/null +++ b/python/m5/objects/BadDevice.mpy @@ -0,0 +1,5 @@ +from Device import PioDevice + +simobj BadDevice(PioDevice): + type = 'BadDevice' + devicename = Param.String("Name of device to error on") diff --git a/python/m5/objects/BaseCPU.mpy b/python/m5/objects/BaseCPU.mpy new file mode 100644 index 000000000..484fcccd6 --- /dev/null +++ b/python/m5/objects/BaseCPU.mpy @@ -0,0 +1,25 @@ +simobj BaseCPU(SimObject): + type = 'BaseCPU' + abstract = True + icache = Param.BaseMem(NULL, "L1 instruction cache object") + dcache = Param.BaseMem(NULL, "L1 data cache object") + + if Bool._convert(env.get('FULL_SYSTEM', 'False')): + dtb = Param.AlphaDTB("Data TLB") + itb = Param.AlphaITB("Instruction TLB") + mem = Param.FunctionalMemory("memory") + system = Param.BaseSystem(Super, "system object") + else: + workload = VectorParam.Process("processes to run") + + max_insts_all_threads = Param.Counter(0, + "terminate when all threads have reached this inst count") + max_insts_any_thread = Param.Counter(0, + "terminate when any thread reaches this inst count") + max_loads_all_threads = Param.Counter(0, + "terminate when all threads have reached this load count") + max_loads_any_thread = Param.Counter(0, + "terminate when any thread reaches this load count") + + defer_registration = Param.Bool(False, + "defer registration with system (for sampling)") diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy new file mode 100644 index 000000000..98a422e30 --- /dev/null +++ b/python/m5/objects/BaseCache.mpy @@ -0,0 +1,38 @@ +from BaseMem import BaseMem + +simobj BaseCache(BaseMem): + type = 'BaseCache' + adaptive_compression = Param.Bool(False, + "Use an adaptive compression scheme") + assoc = Param.Int("associativity") + block_size = Param.Int("block size in bytes") + compressed_bus = Param.Bool(False, + "This cache connects to a compressed memory") + compression_latency = Param.Int(0, + "Latency in cycles of compression algorithm") + do_copy = Param.Bool(False, "perform fast copies in the cache") + hash_delay = Param.Int(1, "time in cycles of hash access") + in_bus = Param.Bus(NULL, "incoming bus object") + lifo = Param.Bool(False, + "whether this NIC partition should use LIFO repl. policy") + max_miss_count = Param.Counter(0, + "number of misses to handle before calling exit") + mshrs = Param.Int("number of MSHRs (max outstanding requests)") + out_bus = Param.Bus("outgoing bus object") + prioritizeRequests = Param.Bool(False, + "always service demand misses first") + protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use") + repl = Param.Repl(NULL, "replacement policy") + size = Param.Int("capacity in bytes") + split = Param.Bool(False, "whether or not this cache is split") + split_size = Param.Int(0, + "How many ways of the cache belong to CPU/LRU partition") + store_compressed = Param.Bool(False, + "Store compressed data in the cache") + subblock_size = Param.Int(0, + "Size of subblock in IIC used for compression") + tgts_per_mshr = Param.Int("max number of accesses per MSHR") + trace_addr = Param.Addr(0, "address to trace") + two_queue = Param.Bool(False, + "whether the lifo should have two queue replacement") + write_buffers = Param.Int(8, "number of write buffers") diff --git a/python/m5/objects/BaseSystem.mpy b/python/m5/objects/BaseSystem.mpy new file mode 100644 index 000000000..1cbdf4e99 --- /dev/null +++ b/python/m5/objects/BaseSystem.mpy @@ -0,0 +1,15 @@ +simobj BaseSystem(SimObject): + type = 'BaseSystem' + abstract = True + memctrl = Param.MemoryController(Super, "memory controller") + physmem = Param.PhysicalMemory(Super, "phsyical memory") + kernel = Param.String("file that contains the kernel code") + console = Param.String("file that contains the console code") + pal = Param.String("file that contains palcode") + readfile = Param.String("", "file to read startup script from") + init_param = Param.UInt64(0, "numerical value to pass into simulator") + boot_osflags = Param.String("a", "boot flags to pass to the kernel") + system_type = Param.UInt64("Type of system we are emulating") + system_rev = Param.UInt64("Revision of system we are emulating") + bin = Param.Bool(False, "is this system binned") + binned_fns = VectorParam.String([], "functions broken down and binned") diff --git a/python/m5/objects/Bus.mpy b/python/m5/objects/Bus.mpy new file mode 100644 index 000000000..025d69785 --- /dev/null +++ b/python/m5/objects/Bus.mpy @@ -0,0 +1,6 @@ +from BaseHier import BaseHier + +simobj Bus(BaseHier): + type = 'Bus' + clock_ratio = Param.Int("ratio of CPU to bus frequency") + width = Param.Int("bus width in bytes") diff --git a/python/m5/objects/CoherenceProtocol.mpy b/python/m5/objects/CoherenceProtocol.mpy new file mode 100644 index 000000000..f3b0026b7 --- /dev/null +++ b/python/m5/objects/CoherenceProtocol.mpy @@ -0,0 +1,6 @@ +class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi'] + +simobj CoherenceProtocol(SimObject): + type = 'CoherenceProtocol' + do_upgrades = Param.Bool(True, "use upgrade transactions?") + protocol = Param.Coherence("name of coherence protocol") diff --git a/python/m5/objects/Device.mpy b/python/m5/objects/Device.mpy new file mode 100644 index 000000000..47f8db1cb --- /dev/null +++ b/python/m5/objects/Device.mpy @@ -0,0 +1,33 @@ +from FunctionalMemory import FunctionalMemory + +# This device exists only because there are some devices that I don't +# want to have a Platform parameter because it would cause a cycle in +# the C++ that cannot be easily solved. +# +# The real solution to this problem is to pass the ParamXXX structure +# to the constructor, but with the express condition that SimObject +# parameter values are not to be available at construction time. If +# some further configuration must be done, it must be done during the +# initialization phase at which point all SimObject pointers will be +# valid. +simobj FooPioDevice(FunctionalMemory): + type = 'PioDevice' + abstract = True + addr = Param.Addr("Device Address") + mmu = Param.MemoryController(Super, "Memory Controller") + io_bus = Param.Bus(NULL, "The IO Bus to attach to") + pio_latency = Param.Tick(1, "Programmed IO latency in bus cycles") + +simobj FooDmaDevice(FooPioDevice): + type = 'DmaDevice' + abstract = True + +simobj PioDevice(FooPioDevice): + type = 'PioDevice' + abstract = True + platform = Param.Platform(Super, "Platform") + +simobj DmaDevice(PioDevice): + type = 'DmaDevice' + abstract = True + diff --git a/python/m5/objects/DiskImage.mpy b/python/m5/objects/DiskImage.mpy new file mode 100644 index 000000000..80ef7b072 --- /dev/null +++ b/python/m5/objects/DiskImage.mpy @@ -0,0 +1,14 @@ +simobj DiskImage(SimObject): + type = 'DiskImage' + abstract = True + image_file = Param.String("disk image file") + read_only = Param.Bool(False, "read only image") + +simobj RawDiskImage(DiskImage): + type = 'RawDiskImage' + +simobj CowDiskImage(DiskImage): + type = 'CowDiskImage' + child = Param.DiskImage("child image") + table_size = Param.Int(65536, "initial table size") + image_file = '' diff --git a/python/m5/objects/Ethernet.mpy b/python/m5/objects/Ethernet.mpy new file mode 100644 index 000000000..088df4b93 --- /dev/null +++ b/python/m5/objects/Ethernet.mpy @@ -0,0 +1,86 @@ +from Device import DmaDevice +from Pci import PciDevice + +simobj EtherInt(SimObject): + type = 'EtherInt' + abstract = True + peer = Param.EtherInt(NULL, "peer interface") + +simobj EtherLink(SimObject): + type = 'EtherLink' + int1 = Param.EtherInt("interface 1") + int2 = Param.EtherInt("interface 2") + delay = Param.Tick(0, "transmit delay of packets in us") + speed = Param.Tick(100000000, "link speed in bits per second") + dump = Param.EtherDump(NULL, "dump object") + +simobj EtherBus(SimObject): + type = 'EtherBus' + loopback = Param.Bool(True, + "send packet back to the interface from which it came") + dump = Param.EtherDump(NULL, "dump object") + speed = Param.UInt64(100000000, "bus speed in bits per second") + +simobj EtherTap(EtherInt): + type = 'EtherTap' + bufsz = Param.Int(10000, "tap buffer size") + dump = Param.EtherDump(NULL, "dump object") + port = Param.UInt16(3500, "tap port") + +simobj EtherDump(SimObject): + type = 'EtherDump' + file = Param.String("dump file") + +simobj EtherDev(DmaDevice): + type = 'EtherDev' + hardware_address = Param.EthernetAddr(NextEthernetAddr, + "Ethernet Hardware Address") + + dma_data_free = Param.Bool(False, "DMA of Data is free") + dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") + dma_read_delay = Param.Tick(0, "fixed delay for dma reads") + dma_read_factor = Param.Tick(0, "multiplier for dma reads") + dma_write_delay = Param.Tick(0, "fixed delay for dma writes") + dma_write_factor = Param.Tick(0, "multiplier for dma writes") + + rx_filter = Param.Bool(True, "Enable Receive Filter") + rx_delay = Param.Tick(1000, "Receive Delay") + tx_delay = Param.Tick(1000, "Transmit Delay") + + intr_delay = Param.Tick(0, "Interrupt Delay in microseconds") + payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") + physmem = Param.PhysicalMemory(Super, "Physical Memory") + tlaser = Param.Turbolaser(Super, "Turbolaser") + +simobj NSGigE(PciDevice): + type = 'NSGigE' + hardware_address = Param.EthernetAddr(NextEthernetAddr, + "Ethernet Hardware Address") + + dma_data_free = Param.Bool(False, "DMA of Data is free") + dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") + dma_read_delay = Param.Tick(0, "fixed delay for dma reads") + dma_read_factor = Param.Tick(0, "multiplier for dma reads") + dma_write_delay = Param.Tick(0, "fixed delay for dma writes") + dma_write_factor = Param.Tick(0, "multiplier for dma writes") + + rx_filter = Param.Bool(True, "Enable Receive Filter") + rx_delay = Param.Tick(1000, "Receive Delay") + tx_delay = Param.Tick(1000, "Transmit Delay") + + rx_fifo_size = Param.Int(131072, "max size in bytes of rxFifo") + tx_fifo_size = Param.Int(131072, "max size in bytes of txFifo") + + intr_delay = Param.Tick(0, "Interrupt Delay in microseconds") + payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") + physmem = Param.PhysicalMemory(Super, "Physical Memory") + +simobj EtherDevInt(EtherInt): + type = 'EtherDevInt' + device = Param.EtherDev("Ethernet device of this interface") + +simobj NSGigEInt(EtherInt): + type = 'NSGigEInt' + device = Param.NSGigE("Ethernet device of this interface") + + diff --git a/python/m5/objects/Ide.mpy b/python/m5/objects/Ide.mpy new file mode 100644 index 000000000..ce760ad96 --- /dev/null +++ b/python/m5/objects/Ide.mpy @@ -0,0 +1,14 @@ +from Pci import PciDevice + +class IdeID(Enum): vals = ['master', 'slave'] + +simobj IdeDisk(SimObject): + type = 'IdeDisk' + delay = Param.Tick(1, "Fixed disk delay in microseconds") + driveID = Param.IdeID('master', "Drive ID") + image = Param.DiskImage("Disk image") + physmem = Param.PhysicalMemory(Super, "Physical memory") + +simobj IdeController(PciDevice): + type = 'IdeController' + disks = VectorParam.IdeDisk("IDE disks attached to this controller") diff --git a/python/m5/objects/IntrControl.mpy b/python/m5/objects/IntrControl.mpy new file mode 100644 index 000000000..1ef5a17ee --- /dev/null +++ b/python/m5/objects/IntrControl.mpy @@ -0,0 +1,3 @@ +simobj IntrControl(SimObject): + type = 'IntrControl' + cpu = Param.BaseCPU(Super, "the cpu") diff --git a/python/m5/objects/MemTest.mpy b/python/m5/objects/MemTest.mpy new file mode 100644 index 000000000..af14ed9c3 --- /dev/null +++ b/python/m5/objects/MemTest.mpy @@ -0,0 +1,18 @@ +simobj MemTest(SimObject): + type = 'MemTest' + cache = Param.BaseCache("L1 cache") + check_mem = Param.FunctionalMemory("check memory") + main_mem = Param.FunctionalMemory("hierarchical memory") + max_loads = Param.Counter("number of loads to execute") + memory_size = Param.Int(65536, "memory size") + percent_copies = Param.Percent(0, "target copy percentage") + percent_dest_unaligned = Param.Percent(50, + "percent of copy dest address that are unaligned") + percent_reads = Param.Percent(65, "target read percentage") + percent_source_unaligned = Param.Percent(50, + "percent of copy source address that are unaligned") + percent_uncacheable = Param.Percent(10, + "target uncacheable percentage") + progress_interval = Param.Counter(1000000, + "progress report interval (in accesses)") + trace_addr = Param.Addr(0, "address to trace") diff --git a/python/m5/objects/Pci.mpy b/python/m5/objects/Pci.mpy new file mode 100644 index 000000000..caa3c52ff --- /dev/null +++ b/python/m5/objects/Pci.mpy @@ -0,0 +1,52 @@ +from Device import FooPioDevice, DmaDevice + +simobj PciConfigData(FooPioDevice): + type = 'PciConfigData' + addr = 0xffffffffffffffffL + VendorID = Param.UInt16("Vendor ID") + DeviceID = Param.UInt16("Device ID") + Command = Param.UInt16(0, "Command") + Status = Param.UInt16(0, "Status") + Revision = Param.UInt8(0, "Device") + ProgIF = Param.UInt8(0, "Programming Interface") + SubClassCode = Param.UInt8(0, "Sub-Class Code") + ClassCode = Param.UInt8(0, "Class Code") + CacheLineSize = Param.UInt8(0, "System Cacheline Size") + LatencyTimer = Param.UInt8(0, "PCI Latency Timer") + HeaderType = Param.UInt8(0, "PCI Header Type") + BIST = Param.UInt8(0, "Built In Self Test") + + BAR0 = Param.UInt32(0x00, "Base Address Register 0") + BAR1 = Param.UInt32(0x00, "Base Address Register 1") + BAR2 = Param.UInt32(0x00, "Base Address Register 2") + BAR3 = Param.UInt32(0x00, "Base Address Register 3") + BAR4 = Param.UInt32(0x00, "Base Address Register 4") + BAR5 = Param.UInt32(0x00, "Base Address Register 5") + BAR0Size = Param.UInt32(0, "Base Address Register 0 Size") + BAR1Size = Param.UInt32(0, "Base Address Register 1 Size") + BAR2Size = Param.UInt32(0, "Base Address Register 2 Size") + BAR3Size = Param.UInt32(0, "Base Address Register 3 Size") + BAR4Size = Param.UInt32(0, "Base Address Register 4 Size") + BAR5Size = Param.UInt32(0, "Base Address Register 5 Size") + + CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure") + SubsystemID = Param.UInt16(0x00, "Subsystem ID") + SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID") + ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address") + InterruptLine = Param.UInt8(0x00, "Interrupt Line") + InterruptPin = Param.UInt8(0x00, "Interrupt Pin") + MaximumLatency = Param.UInt8(0x00, "Maximum Latency") + MinimumGrant = Param.UInt8(0x00, "Minimum Grant") + +simobj PciConfigAll(FooPioDevice): + type = 'PciConfigAll' + +simobj PciDevice(DmaDevice): + type = 'PciDevice' + abstract = True + pci_bus = Param.Int("PCI bus") + pci_dev = Param.Int("PCI device number") + pci_func = Param.Int("PCI function code") + configdata = Param.PciConfigData(Super, "PCI Config data") + configspace = Param.PciConfigAll(Super, "PCI Configspace") + addr = 0xffffffffffffffffL diff --git a/python/m5/objects/PhysicalMemory.mpy b/python/m5/objects/PhysicalMemory.mpy new file mode 100644 index 000000000..d1e4ad4b4 --- /dev/null +++ b/python/m5/objects/PhysicalMemory.mpy @@ -0,0 +1,7 @@ +from FunctionalMemory import FunctionalMemory + +simobj PhysicalMemory(FunctionalMemory): + type = 'PhysicalMemory' + range = Param.AddrRange("Device Address") + file = Param.String('', "memory mapped file") + mmu = Param.MemoryController(Super, "Memory Controller") diff --git a/python/m5/objects/Platform.mpy b/python/m5/objects/Platform.mpy new file mode 100644 index 000000000..d0510eaf8 --- /dev/null +++ b/python/m5/objects/Platform.mpy @@ -0,0 +1,5 @@ +simobj Platform(SimObject): + type = 'Platform' + abstract = True + interrupt_frequency = Param.Tick(1200, "frequency of interrupts") + intrctrl = Param.IntrControl(Super, "interrupt controller") diff --git a/python/m5/objects/Process.mpy b/python/m5/objects/Process.mpy new file mode 100644 index 000000000..6a91c09c2 --- /dev/null +++ b/python/m5/objects/Process.mpy @@ -0,0 +1,15 @@ +simobj Process(SimObject): + type = 'Process' + abstract = True + output = Param.String('cout', 'filename for stdout/stderr') + +simobj LiveProcess(Process): + type = 'LiveProcess' + cmd = VectorParam.String("command line (executable plus arguments)") + env = VectorParam.String('', "environment settings") + input = Param.String('cin', "filename for stdin") + +simobj EioProcess(Process): + type = 'EioProcess' + chkpt = Param.String('', "EIO checkpoint file name (optional)") + file = Param.String("EIO trace file name") diff --git a/python/m5/objects/Repl.mpy b/python/m5/objects/Repl.mpy new file mode 100644 index 000000000..fff5a2a02 --- /dev/null +++ b/python/m5/objects/Repl.mpy @@ -0,0 +1,9 @@ +simobj Repl(SimObject): + type = 'Repl' + abstract = True + +simobj GenRepl(Repl): + type = 'GenRepl' + fresh_res = Param.Int("associativity") + num_pools = Param.Int("capacity in bytes") + pool_res = Param.Int("block size in bytes") diff --git a/python/m5/objects/Root.mpy b/python/m5/objects/Root.mpy new file mode 100644 index 000000000..0e531054b --- /dev/null +++ b/python/m5/objects/Root.mpy @@ -0,0 +1,15 @@ +from HierParams import HierParams +from Serialize import Serialize +from Statistics import Statistics +from Trace import Trace + +simobj Root(SimObject): + type = 'Root' + frequency = Param.Tick(200000000, "tick frequency") + output_file = Param.String('cout', "file to dump simulator output to") + full_system = Param.Bool("Full system simulation?") + hier = HierParams(do_data = False, do_events = True) + checkpoint = Param.String('', "Checkpoint file") + stats = Statistics() + trace = Trace() + serialize = Serialize() diff --git a/python/m5/objects/SimConsole.mpy b/python/m5/objects/SimConsole.mpy new file mode 100644 index 000000000..fb74f1775 --- /dev/null +++ b/python/m5/objects/SimConsole.mpy @@ -0,0 +1,11 @@ +simobj ConsoleListener(SimObject): + type = 'ConsoleListener' + port = Param.UInt16(3456, "listen port") + +simobj SimConsole(SimObject): + type = 'SimConsole' + append_name = Param.Bool(True, "append name() to filename") + intr_control = Param.IntrControl(Super, "interrupt controller") + listener = Param.ConsoleListener("console listener") + number = Param.Int(0, "console number") + output = Param.String('console', "file to dump output to") diff --git a/python/m5/objects/SimpleDisk.mpy b/python/m5/objects/SimpleDisk.mpy new file mode 100644 index 000000000..c4dd5435b --- /dev/null +++ b/python/m5/objects/SimpleDisk.mpy @@ -0,0 +1,4 @@ +simobj SimpleDisk(SimObject): + type = 'SimpleDisk' + disk = Param.DiskImage("Disk Image") + physmem = Param.PhysicalMemory(Super, "Physical Memory") diff --git a/python/m5/objects/Tsunami.mpy b/python/m5/objects/Tsunami.mpy new file mode 100644 index 000000000..cfe23977e --- /dev/null +++ b/python/m5/objects/Tsunami.mpy @@ -0,0 +1,25 @@ +from Device import FooPioDevice +from Platform import Platform + +simobj Tsunami(Platform): + type = 'Tsunami' + pciconfig = Param.PciConfigAll("PCI configuration") + system = Param.BaseSystem(Super, "system") + interrupt_frequency = Param.Int(1024, "frequency of interrupts") + +simobj TsunamiCChip(FooPioDevice): + type = 'TsunamiCChip' + tsunami = Param.Tsunami(Super, "Tsunami") + +simobj TsunamiFake(FooPioDevice): + type = 'TsunamiFake' + +simobj TsunamiIO(FooPioDevice): + type = 'TsunamiIO' + time = Param.UInt64(1136073600, + "System time to use (0 for actual time, default is 1/1/06)") + tsunami = Param.Tsunami(Super, "Tsunami") + +simobj TsunamiPChip(FooPioDevice): + type = 'TsunamiPChip' + tsunami = Param.Tsunami(Super, "Tsunami") diff --git a/python/m5/objects/Uart.mpy b/python/m5/objects/Uart.mpy new file mode 100644 index 000000000..76ee8805f --- /dev/null +++ b/python/m5/objects/Uart.mpy @@ -0,0 +1,6 @@ +from Device import PioDevice + +simobj Uart(PioDevice): + type = 'Uart' + console = Param.SimConsole(Super, "The console") + size = Param.Addr(0x8, "Device size") |