4 files changed, 5 insertions, 5 deletions
diff --git a/python/m5/objects/BaseCache.mpy b/python/m5/objects/BaseCache.mpy
index 98a422e30..b9986917f 100644
--- a/python/m5/objects/BaseCache.mpy
+++ b/python/m5/objects/BaseCache.mpy
@@ -23,7 +23,7 @@ simobj BaseCache(BaseMem):
         "always service demand misses first")
     protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
     repl = Param.Repl(NULL, "replacement policy")
-    size = Param.Int("capacity in bytes")
+    size = Param.MemorySize("capacity in bytes")
     split = Param.Bool(False, "whether or not this cache is split")
     split_size = Param.Int(0,
         "How many ways of the cache belong to CPU/LRU partition")
diff --git a/python/m5/objects/Bus.mpy b/python/m5/objects/Bus.mpy
index 025d69785..aa12f757a 100644
--- a/python/m5/objects/Bus.mpy
+++ b/python/m5/objects/Bus.mpy
@@ -2,5 +2,5 @@ from BaseHier import BaseHier
 
 simobj Bus(BaseHier):
     type = 'Bus'
-    clock_ratio = Param.Int("ratio of CPU to bus frequency")
+    clock_ratio = Param.ClockPeriod("ratio of CPU to bus frequency")
     width = Param.Int("bus width in bytes")
diff --git a/python/m5/objects/Ethernet.mpy b/python/m5/objects/Ethernet.mpy
index cd251f36d..3acd8d04d 100644
--- a/python/m5/objects/Ethernet.mpy
+++ b/python/m5/objects/Ethernet.mpy
@@ -68,8 +68,8 @@ simobj NSGigE(PciDevice):
     rx_delay = Param.Tick(1000, "Receive Delay")
     tx_delay = Param.Tick(1000, "Transmit Delay")
 
-    rx_fifo_size = Param.Int(131072, "max size in bytes of rxFifo")
-    tx_fifo_size = Param.Int(131072, "max size in bytes of txFifo")
+    rx_fifo_size = Param.MemorySize('128kB', "max size in bytes of rxFifo")
+    tx_fifo_size = Param.MemorySize('128kB', "max size in bytes of txFifo")
 
     intr_delay = Param.Tick(0, "Interrupt Delay in microseconds")
     payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
diff --git a/python/m5/objects/Root.mpy b/python/m5/objects/Root.mpy
index 0e531054b..c535bd2dc 100644
--- a/python/m5/objects/Root.mpy
+++ b/python/m5/objects/Root.mpy
@@ -5,7 +5,7 @@ from Trace import Trace
 
 simobj Root(SimObject):
     type = 'Root'
-    frequency = Param.Tick(200000000, "tick frequency")
+    frequency = Param.RootFrequency('200MHz', "tick frequency")
     output_file = Param.String('cout', "file to dump simulator output to")
     full_system = Param.Bool("Full system simulation?")
     hier = HierParams(do_data = False, do_events = True)