5 files changed, 21 insertions, 21 deletions
diff --git a/python/m5/objects/Device.py b/python/m5/objects/Device.py
index cda3b1824..2a71bbc65 100644
--- a/python/m5/objects/Device.py
+++ b/python/m5/objects/Device.py
@@ -12,3 +12,7 @@ class BasicPioDevice(PioDevice):
     abstract = True
     pio_addr = Param.Addr("Device Address")
     pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
+
+class DmaDevice(PioDevice):
+    type = 'DmaDevice'
+    abstract = True
diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py
index 22714e15c..0667fc6d7 100644
--- a/python/m5/objects/Ethernet.py
+++ b/python/m5/objects/Ethernet.py
@@ -67,14 +67,10 @@ class EtherDevBase(PciDevice):
 
     clock = Param.Clock('0ns', "State machine processor frequency")
 
-    physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
-
-    payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
     dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
     dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
     dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
     dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
-    dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
 
     rx_delay = Param.Latency('1us', "Receive Delay")
     tx_delay = Param.Latency('1us', "Transmit Delay")
@@ -92,6 +88,7 @@ class NSGigE(EtherDevBase):
 
     dma_data_free = Param.Bool(False, "DMA of Data is free")
     dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
+    dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
 
 
 class NSGigEInt(EtherInt):
diff --git a/python/m5/objects/Ide.py b/python/m5/objects/Ide.py
index 6855ec653..2403e6d36 100644
--- a/python/m5/objects/Ide.py
+++ b/python/m5/objects/Ide.py
@@ -8,7 +8,6 @@ class IdeDisk(SimObject):
     delay = Param.Latency('1us', "Fixed disk delay in microseconds")
     driveID = Param.IdeID('master', "Drive ID")
     image = Param.DiskImage("Disk image")
-    physmem = Param.PhysicalMemory(Parent.any, "Physical memory")
 
 class IdeController(PciDevice):
     type = 'IdeController'
diff --git a/python/m5/objects/Pci.py b/python/m5/objects/Pci.py
index f2ccce09f..85cefcd44 100644
--- a/python/m5/objects/Pci.py
+++ b/python/m5/objects/Pci.py
@@ -1,6 +1,5 @@
 from m5 import *
-from Device import BasicPioDevice
-#, DmaDevice
+from Device import BasicPioDevice, DmaDevice
 
 class PciConfigData(SimObject):
     type = 'PciConfigData'
@@ -42,15 +41,15 @@ class PciConfigData(SimObject):
 class PciConfigAll(BasicPioDevice):
     type = 'PciConfigAll'
 
-#class PciDevice(DmaDevice):
-#    type = 'PciDevice'
-#    abstract = True
-#    addr = 0xffffffffL
-#    pci_bus = Param.Int("PCI bus")
-#    pci_dev = Param.Int("PCI device number")
-#    pci_func = Param.Int("PCI function code")
-#    configdata = Param.PciConfigData(Parent.any, "PCI Config data")
-#    configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
-#
-#class PciFake(PciDevice):
-#    type = 'PciFake'
+class PciDevice(DmaDevice):
+    type = 'PciDevice'
+    abstract = True
+    pci_bus = Param.Int("PCI bus")
+    pci_dev = Param.Int("PCI device number")
+    pci_func = Param.Int("PCI function code")
+    pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
+    configdata = Param.PciConfigData(Parent.any, "PCI Config data")
+    configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
+
+class PciFake(PciDevice):
+    type = 'PciFake'
diff --git a/python/m5/objects/PhysicalMemory.py b/python/m5/objects/PhysicalMemory.py
index b69c969cb..e59e94e9b 100644
--- a/python/m5/objects/PhysicalMemory.py
+++ b/python/m5/objects/PhysicalMemory.py
@@ -1,7 +1,8 @@
 from m5 import *
-from Memory import Memory
+from MemObject import *
 
-class PhysicalMemory(Memory):
+class PhysicalMemory(MemObject):
     type = 'PhysicalMemory'
     range = Param.AddrRange("Device Address")
     file = Param.String('', "memory mapped file")
+    latency = Param.Latency('10ns', "latency of an access")