diff options
Diffstat (limited to 'python/m5')
| -rw-r--r-- | python/m5/objects/BaseCPU.py | 4 | ||||
| -rw-r--r-- | python/m5/objects/Ethernet.py | 1 | ||||
| -rw-r--r-- | python/m5/objects/MemObject.py | 5 | ||||
| -rw-r--r-- | python/m5/objects/PhysicalMemory.py | 7 | ||||
| -rw-r--r-- | python/m5/objects/Process.py | 10 | ||||
| -rw-r--r-- | python/m5/objects/Root.py | 4 | ||||
| -rw-r--r-- | python/m5/objects/System.py | 17 |
7 files changed, 29 insertions, 19 deletions
diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py index a90203729..07cb850f1 100644 --- a/python/m5/objects/BaseCPU.py +++ b/python/m5/objects/BaseCPU.py @@ -2,16 +2,14 @@ from m5 import * class BaseCPU(SimObject): type = 'BaseCPU' abstract = True - icache = Param.BaseMem(NULL, "L1 instruction cache object") - dcache = Param.BaseMem(NULL, "L1 data cache object") if build_env['FULL_SYSTEM']: dtb = Param.AlphaDTB("Data TLB") itb = Param.AlphaITB("Instruction TLB") - mem = Param.FunctionalMemory("memory") system = Param.System(Parent.any, "system object") cpu_id = Param.Int(-1, "CPU identifier") else: + mem = Param.Memory(Parent.any, "memory") workload = VectorParam.Process("processes to run") max_insts_all_threads = Param.Counter(0, diff --git a/python/m5/objects/Ethernet.py b/python/m5/objects/Ethernet.py index 6113e656f..22714e15c 100644 --- a/python/m5/objects/Ethernet.py +++ b/python/m5/objects/Ethernet.py @@ -69,7 +69,6 @@ class EtherDevBase(PciDevice): physmem = Param.PhysicalMemory(Parent.any, "Physical Memory") - hier = Param.HierParams(Parent.any, "Hierarchy global variables") payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload") dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") dma_read_factor = Param.Latency('0us', "multiplier for dma reads") diff --git a/python/m5/objects/MemObject.py b/python/m5/objects/MemObject.py new file mode 100644 index 000000000..4d68243e6 --- /dev/null +++ b/python/m5/objects/MemObject.py @@ -0,0 +1,5 @@ +from m5 import * + +class MemObject(SimObject): + type = 'MemObject' + abstract = True diff --git a/python/m5/objects/PhysicalMemory.py b/python/m5/objects/PhysicalMemory.py index f50937ee6..b0aba1a7d 100644 --- a/python/m5/objects/PhysicalMemory.py +++ b/python/m5/objects/PhysicalMemory.py @@ -1,8 +1,9 @@ from m5 import * -from FunctionalMemory import FunctionalMemory +from Memory import Memory -class PhysicalMemory(FunctionalMemory): +class PhysicalMemory(Memory): type = 'PhysicalMemory' range = Param.AddrRange("Device Address") file = Param.String('', "memory mapped file") - mmu = Param.MemoryController(Parent.any, "Memory Controller") + if build_env['FULL_SYSTEM']: + mmu = Param.MemoryController(Parent.any, "Memory Controller") diff --git a/python/m5/objects/Process.py b/python/m5/objects/Process.py index b4ccc1bec..60b00229e 100644 --- a/python/m5/objects/Process.py +++ b/python/m5/objects/Process.py @@ -3,6 +3,7 @@ class Process(SimObject): type = 'Process' abstract = True output = Param.String('cout', 'filename for stdout/stderr') + system = Param.System(Parent.any, "system process will run on") class LiveProcess(Process): type = 'LiveProcess' @@ -11,6 +12,15 @@ class LiveProcess(Process): env = VectorParam.String('', "environment settings") input = Param.String('cin', "filename for stdin") +class AlphaLiveProcess(LiveProcess): + type = 'AlphaLiveProcess' + +class SparcLiveProcess(LiveProcess): + type = 'SparcLiveProcess' + +class MipsLiveProcess(LiveProcess): + type = 'MipsLiveProcess' + class EioProcess(Process): type = 'EioProcess' chkpt = Param.String('', "EIO checkpoint file name (optional)") diff --git a/python/m5/objects/Root.py b/python/m5/objects/Root.py index 23b13fc67..f51516098 100644 --- a/python/m5/objects/Root.py +++ b/python/m5/objects/Root.py @@ -1,5 +1,4 @@ from m5 import * -from HierParams import HierParams from Serialize import Serialize from Statistics import Statistics from Trace import Trace @@ -13,12 +12,9 @@ class Root(SimObject): "print a progress message every n ticks (0 = never)") output_file = Param.String('cout', "file to dump simulator output to") checkpoint = Param.String('', "checkpoint file to load") -# hier = Param.HierParams(HierParams(do_data = False, do_events = True), -# "shared memory hierarchy parameters") # stats = Param.Statistics(Statistics(), "statistics object") # trace = Param.Trace(Trace(), "trace object") # serialize = Param.Serialize(Serialize(), "checkpoint generation options") - hier = HierParams(do_data = False, do_events = True) stats = Statistics() trace = Trace() exetrace = ExecutionTrace() diff --git a/python/m5/objects/System.py b/python/m5/objects/System.py index 5925cadf5..2959c1d1a 100644 --- a/python/m5/objects/System.py +++ b/python/m5/objects/System.py @@ -2,15 +2,16 @@ from m5 import * class System(SimObject): type = 'System' - boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency, - "boot processor frequency") - memctrl = Param.MemoryController(Parent.any, "memory controller") physmem = Param.PhysicalMemory(Parent.any, "phsyical memory") - init_param = Param.UInt64(0, "numerical value to pass into simulator") - bin = Param.Bool(False, "is this system binned") - binned_fns = VectorParam.String([], "functions broken down and binned") - kernel = Param.String("file that contains the kernel code") - readfile = Param.String("", "file to read startup script from") + if build_env['FULL_SYSTEM']: + boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency, + "boot processor frequency") + memctrl = Param.MemoryController(Parent.any, "memory controller") + init_param = Param.UInt64(0, "numerical value to pass into simulator") + bin = Param.Bool(False, "is this system binned") + binned_fns = VectorParam.String([], "functions broken down and binned") + kernel = Param.String("file that contains the kernel code") + readfile = Param.String("", "file to read startup script from") class AlphaSystem(System): type = 'AlphaSystem' |