diff options
Diffstat (limited to 'sim/intr_control.hh')
-rw-r--r-- | sim/intr_control.hh | 61 |
1 files changed, 0 insertions, 61 deletions
diff --git a/sim/intr_control.hh b/sim/intr_control.hh deleted file mode 100644 index 660d6d704..000000000 --- a/sim/intr_control.hh +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2003 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __INTR_CONTROL_HH__ -#define __INTR_CONTROL_HH__ - -#include "misc.hh" -#include "base_cpu.hh" -#include "sim_object.hh" - -class IntrControl : public SimObject -{ - public: - BaseCPU *cpu; - IntrControl(const std::string &name, BaseCPU *c); - - void clear(int int_num, int index = 0); - void post(int int_num, int index = 0); -}; - -inline void -IntrControl::post(int int_num, int index) -{ cpu->post_interrupt(int_num, index); } - -inline void -IntrControl::clear(int int_num, int index) -{ cpu->clear_interrupt(int_num, index); } - -#endif // __INTR_CONTROL_HH__ - - - - - - - |