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-rw-r--r--sim/main.cc4
-rw-r--r--sim/process.cc24
-rw-r--r--sim/pseudo_inst.cc2
-rw-r--r--sim/sim_object.cc20
-rw-r--r--sim/sim_object.hh2
-rw-r--r--sim/system.cc30
-rw-r--r--sim/system.hh16
-rw-r--r--sim/vptr.hh12
8 files changed, 75 insertions, 35 deletions
diff --git a/sim/main.cc b/sim/main.cc
index 6f6143506..aecc171ed 100644
--- a/sim/main.cc
+++ b/sim/main.cc
@@ -355,6 +355,10 @@ main(int argc, char **argv)
echoCommandLine(argc, argv, *outputStream);
ParamContext::showAllContexts(*configStream);
+ // Any objects that can't connect themselves until after construction should
+ // do so now
+ SimObject::connectAll();
+
// Do a second pass to finish initializing the sim objects
SimObject::initAll();
diff --git a/sim/process.cc b/sim/process.cc
index 7b27c4274..ce5833881 100644
--- a/sim/process.cc
+++ b/sim/process.cc
@@ -39,7 +39,7 @@
#include "config/full_system.hh"
#include "cpu/exec_context.hh"
#include "mem/page_table.hh"
-#include "mem/mem_object.hh"
+#include "mem/physical.hh"
#include "mem/translating_port.hh"
#include "sim/builder.hh"
#include "sim/process.hh"
@@ -153,21 +153,11 @@ Process::startup()
// mark this context as active so it will start ticking.
xc->activate(0);
- // Here we are grabbing the memory port of the CPU hosting the
- // initial execution context for initialization. In the long run
- // this is not what we want, since it means that all
- // initialization accesses (e.g., loading object file sections)
- // will be done a cache block at a time through the CPU's cache.
- // We really want something more like:
- //
- // memport = system->physmem->getPort();
- // myPort.setPeer(memport);
- // memport->setPeer(&myPort);
- // initVirtMem = new TranslatingPort(myPort, pTable);
- //
- // but we need our own dummy port "myPort" that doesn't exist.
- // In the short term it works just fine though.
- initVirtMem = xc->getMemPort();
+ Port *mem_port;
+ mem_port = system->physmem->getPort("functional");
+ initVirtMem = new TranslatingPort(pTable, true);
+ mem_port->setPeer(initVirtMem);
+ initVirtMem->setPeer(mem_port);
}
void
@@ -326,7 +316,7 @@ LiveProcess::argsInit(int intSize, int pageSize)
roundUp(stack_size, pageSize));
// map out initial stack contents
- Addr argv_array_base = stack_min + sizeof(uint64_t); // room for argc
+ Addr argv_array_base = stack_min + intSize; // room for argc
Addr envp_array_base = argv_array_base + argv_array_size;
Addr arg_data_base = envp_array_base + envp_array_size;
Addr env_data_base = arg_data_base + arg_data_size;
diff --git a/sim/pseudo_inst.cc b/sim/pseudo_inst.cc
index e475006e7..3cdc05e78 100644
--- a/sim/pseudo_inst.cc
+++ b/sim/pseudo_inst.cc
@@ -175,7 +175,7 @@ namespace AlphaPseudo
addsymbol(ExecContext *xc, Addr addr, Addr symbolAddr)
{
char symb[100];
- CopyString(xc, symb, symbolAddr, 100);
+ CopyStringOut(xc, symb, symbolAddr, 100);
std::string symbol(symb);
DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
diff --git a/sim/sim_object.cc b/sim/sim_object.cc
index f34e17fe6..151ba68a7 100644
--- a/sim/sim_object.cc
+++ b/sim/sim_object.cc
@@ -88,6 +88,11 @@ SimObject::SimObject(const string &_name)
}
void
+SimObject::connect()
+{
+}
+
+void
SimObject::init()
{
}
@@ -151,6 +156,21 @@ SimObject::regAllStats()
}
//
+// static function: call connect() on all SimObjects.
+//
+void
+SimObject::connectAll()
+{
+ SimObjectList::iterator i = simObjectList.begin();
+ SimObjectList::iterator end = simObjectList.end();
+
+ for (; i != end; ++i) {
+ SimObject *obj = *i;
+ obj->connect();
+ }
+}
+
+//
// static function: call init() on all SimObjects.
//
void
diff --git a/sim/sim_object.hh b/sim/sim_object.hh
index 59d9daf45..5db62dd51 100644
--- a/sim/sim_object.hh
+++ b/sim/sim_object.hh
@@ -78,7 +78,9 @@ class SimObject : public Serializable, protected StartupCallback
// initialization pass of all objects.
// Gets invoked after construction, before unserialize.
virtual void init();
+ virtual void connect();
static void initAll();
+ static void connectAll();
// register statistics for this object
virtual void regStats();
diff --git a/sim/system.cc b/sim/system.cc
index 409e41ead..ca9d68d77 100644
--- a/sim/system.cc
+++ b/sim/system.cc
@@ -1,17 +1,17 @@
+#include "arch/isa_traits.hh"
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
+#include "base/trace.hh"
#include "cpu/exec_context.hh"
+#include "mem/mem_object.hh"
+#include "mem/physical.hh"
#include "sim/builder.hh"
-#include "arch/isa_traits.hh"
#include "sim/byteswap.hh"
#include "sim/system.hh"
-#include "base/trace.hh"
-#include "mem/mem_object.hh"
#if FULL_SYSTEM
+#include "arch/vtophys.hh"
#include "base/remote_gdb.hh"
#include "kern/kernel_stats.hh"
-#include "mem/functional/memory_control.hh"
-#include "arch/vtophys.hh"
#endif
using namespace std;
@@ -24,7 +24,7 @@ int System::numSystemsRunning = 0;
System::System(Params *p)
: SimObject(p->name), physmem(p->physmem), numcpus(0),
#if FULL_SYSTEM
- memctrl(p->memctrl), init_param(p->init_param),
+ init_param(p->init_param),
#else
page_ptr(0),
#endif
@@ -37,6 +37,20 @@ System::System(Params *p)
kernelSymtab = new SymbolTable;
debugSymbolTable = new SymbolTable;
+
+ /**
+ * Get a functional port to memory
+ */
+ Port *mem_port;
+ mem_port = physmem->getPort("functional");
+ functionalPort.setPeer(mem_port);
+ mem_port->setPeer(&functionalPort);
+
+ mem_port = physmem->getPort("functional");
+ virtPort.setPeer(mem_port);
+ mem_port->setPeer(&virtPort);
+
+
/**
* Load the kernel code into memory
*/
@@ -46,7 +60,7 @@ System::System(Params *p)
fatal("Could not load kernel file %s", params()->kernel_path);
// Load program sections into memory
- kernel->loadSections(physmem, true);
+ kernel->loadSections(&functionalPort, LoadAddrMask);
// setup entry points
kernelStart = kernel->textBase();
@@ -228,7 +242,7 @@ DEFINE_SIM_OBJECT_CLASS_NAME("System", System)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(System)
- SimObjectParam<MemObject *> physmem;
+ SimObjectParam<PhysicalMemory *> physmem;
END_DECLARE_SIM_OBJECT_PARAMS(System)
diff --git a/sim/system.hh b/sim/system.hh
index 0f82f81f5..3c2c27bee 100644
--- a/sim/system.hh
+++ b/sim/system.hh
@@ -36,16 +36,17 @@
#include "base/misc.hh"
#include "base/statistics.hh"
#include "cpu/pc_event.hh"
+#include "mem/port.hh"
#include "sim/sim_object.hh"
#if FULL_SYSTEM
#include "kern/system_events.hh"
+#include "mem/vport.hh"
#endif
class BaseCPU;
class ExecContext;
-class MemoryController;
class ObjectFile;
-class MemObject;
+class PhysicalMemory;
#if FULL_SYSTEM
class Platform;
@@ -57,7 +58,7 @@ namespace Kernel { class Binning; }
class System : public SimObject
{
public:
- MemObject *physmem;
+ PhysicalMemory *physmem;
PCEventQueue pcEventQueue;
std::vector<ExecContext *> execContexts;
@@ -72,10 +73,14 @@ class System : public SimObject
}
#if FULL_SYSTEM
- MemoryController *memctrl;
Platform *platform;
uint64_t init_param;
+ /** Port to physical memory used for writing object files into ram at
+ * boot.*/
+ FunctionalPort functionalPort;
+ VirtualPort virtPort;
+
/** kernel symbol table */
SymbolTable *kernelSymtab;
@@ -146,11 +151,10 @@ class System : public SimObject
struct Params
{
std::string name;
- MemObject *physmem;
+ PhysicalMemory *physmem;
#if FULL_SYSTEM
Tick boot_cpu_frequency;
- MemoryController *memctrl;
uint64_t init_param;
bool bin;
std::vector<std::string> binned_fns;
diff --git a/sim/vptr.hh b/sim/vptr.hh
index 0ec452f25..cc57e63f0 100644
--- a/sim/vptr.hh
+++ b/sim/vptr.hh
@@ -96,20 +96,26 @@ class VPtr
operator T *()
{
- void *addr = vtomem(xc, ptr, sizeof(T));
+ panic("Needs to be rewritten\n");
+/* void *addr = vtomem(xc, ptr, sizeof(T));
return (T *)addr;
+ */
}
T *operator->()
{
- void *addr = vtomem(xc, ptr, sizeof(T));
+ panic("Needs to be rewritten\n");
+/* void *addr = vtomem(xc, ptr, sizeof(T));
return (T *)addr;
+ */
}
T &operator*()
{
- void *addr = vtomem(xc, ptr, sizeof(T));
+ panic("Needs to be rewritten\n");
+/* void *addr = vtomem(xc, ptr, sizeof(T));
return *(T *)addr;
+ */
}
};
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-10 16:35:16 +0000