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-rw-r--r--src/arch/alpha/AlphaTLB.py6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py
index 559516725..fec245b75 100644
--- a/src/arch/alpha/AlphaTLB.py
+++ b/src/arch/alpha/AlphaTLB.py
@@ -35,8 +35,14 @@ class AlphaTLB(SimObject):
class AlphaDTB(AlphaTLB):
type = 'AlphaDTB'
+ cxx_namespace = 'AlphaISA'
+ cxx_class = 'DTB'
+
size = 64
class AlphaITB(AlphaTLB):
type = 'AlphaITB'
+ cxx_namespace = 'AlphaISA'
+ cxx_class = 'ITB'
+
size = 48