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Diffstat (limited to 'src/arch/alpha/ev5.cc')
-rw-r--r--src/arch/alpha/ev5.cc17
1 files changed, 8 insertions, 9 deletions
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 7595423c3..314b445e0 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -60,7 +60,7 @@ AlphaISA::initCPU(ThreadContext *tc, int cpuId)
tc->setIntReg(16, cpuId);
tc->setIntReg(0, cpuId);
- AlphaFault *reset = new ResetFault;
+ AlphaISA::AlphaFault *reset = new AlphaISA::ResetFault;
tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect());
tc->setNextPC(tc->readPC() + sizeof(MachInst));
@@ -176,7 +176,7 @@ AlphaISA::MiscRegFile::getDataAsid()
}
AlphaISA::MiscReg
-AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc)
+AlphaISA::MiscRegFile::readIpr(int idx, ThreadContext *tc)
{
uint64_t retval = 0; // return value, default 0
@@ -269,12 +269,12 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc)
case AlphaISA::IPR_DTB_IAP:
case AlphaISA::IPR_ITB_IA:
case AlphaISA::IPR_ITB_IAP:
- fault = new UnimplementedOpcodeFault;
+ panic("Tried to read write only register %d\n", idx);
break;
default:
// invalid IPR
- fault = new UnimplementedOpcodeFault;
+ panic("Tried to read from invalid ipr %d\n", idx);
break;
}
@@ -286,13 +286,13 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc)
int break_ipl = -1;
#endif
-Fault
+void
AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
{
uint64_t old;
if (tc->misspeculating())
- return NoFault;
+ return;
switch (idx) {
case AlphaISA::IPR_PALtemp0:
@@ -443,7 +443,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
case AlphaISA::IPR_ITB_PTE_TEMP:
case AlphaISA::IPR_DTB_PTE_TEMP:
// read-only registers
- return new UnimplementedOpcodeFault;
+ panic("Tried to write read only ipr %d\n", idx);
case AlphaISA::IPR_HWINT_CLR:
case AlphaISA::IPR_SL_XMIT:
@@ -547,11 +547,10 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
default:
// invalid IPR
- return new UnimplementedOpcodeFault;
+ panic("Tried to write to invalid ipr %d\n", idx);
}
// no error...
- return NoFault;
}