diff options
Diffstat (limited to 'src/arch/alpha/faults.cc')
-rw-r--r-- | src/arch/alpha/faults.cc | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc index 7417ada5f..845ac0288 100644 --- a/src/arch/alpha/faults.cc +++ b/src/arch/alpha/faults.cc @@ -116,15 +116,15 @@ void AlphaFault::invoke(ThreadContext * tc) // exception restart address if (setRestartAddress() || !(tc->readPC() & 0x3)) - tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, tc->readPC()); + tc->setMiscRegNoEffect(IPR_EXC_ADDR, tc->readPC()); if (skipFaultingInstruction()) { // traps... skip faulting instruction. - tc->setMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR, - tc->readMiscRegNoEffect(AlphaISA::IPR_EXC_ADDR) + 4); + tc->setMiscRegNoEffect(IPR_EXC_ADDR, + tc->readMiscRegNoEffect(IPR_EXC_ADDR) + 4); } - tc->setPC(tc->readMiscRegNoEffect(AlphaISA::IPR_PAL_BASE) + vect()); + tc->setPC(tc->readMiscRegNoEffect(IPR_PAL_BASE) + vect()); tc->setNextPC(tc->readPC() + sizeof(MachInst)); } @@ -144,17 +144,17 @@ void DtbFault::invoke(ThreadContext * tc) if (!tc->misspeculating() && !(reqFlags & VPTE) && !(reqFlags & NO_FAULT)) { // set VA register with faulting address - tc->setMiscRegNoEffect(AlphaISA::IPR_VA, vaddr); + tc->setMiscRegNoEffect(IPR_VA, vaddr); // set MM_STAT register flags - tc->setMiscRegNoEffect(AlphaISA::IPR_MM_STAT, - (((AlphaISA::Opcode(tc->getInst()) & 0x3f) << 11) - | ((AlphaISA::Ra(tc->getInst()) & 0x1f) << 6) + tc->setMiscRegNoEffect(IPR_MM_STAT, + (((Opcode(tc->getInst()) & 0x3f) << 11) + | ((Ra(tc->getInst()) & 0x1f) << 6) | (flags & 0x3f))); // set VA_FORM register with faulting formatted address - tc->setMiscRegNoEffect(AlphaISA::IPR_VA_FORM, - tc->readMiscRegNoEffect(AlphaISA::IPR_MVPTBR) | (vaddr.vpn() << 3)); + tc->setMiscRegNoEffect(IPR_VA_FORM, + tc->readMiscRegNoEffect(IPR_MVPTBR) | (vaddr.vpn() << 3)); } AlphaFault::invoke(tc); @@ -163,10 +163,10 @@ void DtbFault::invoke(ThreadContext * tc) void ItbFault::invoke(ThreadContext * tc) { if (!tc->misspeculating()) { - tc->setMiscRegNoEffect(AlphaISA::IPR_ITB_TAG, pc); - tc->setMiscRegNoEffect(AlphaISA::IPR_IFAULT_VA_FORM, - tc->readMiscRegNoEffect(AlphaISA::IPR_IVPTBR) | - (AlphaISA::VAddr(pc).vpn() << 3)); + tc->setMiscRegNoEffect(IPR_ITB_TAG, pc); + tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM, + tc->readMiscRegNoEffect(IPR_IVPTBR) | + (VAddr(pc).vpn() << 3)); } AlphaFault::invoke(tc); |