1 files changed, 4 insertions, 7 deletions
diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 6375b0bfb..2928f8d65 100644
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -147,8 +147,7 @@ DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
         // on VPTE loads (instead of locking the registers until IPR_VA is
         // read, like the EV5).  The EV6 approach is cleaner and seems to
         // work with EV5 PAL code, but not the other way around.
-        if (!tc->misspeculating() &&
-            reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
+        if (reqFlags.noneSet(Request::VPTE | Request::PREFETCH)) {
             // set VA register with faulting address
             tc->setMiscRegNoEffect(IPR_VA, vaddr);
 
@@ -172,11 +171,9 @@ void
 ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
 {
     if (FullSystem) {
-        if (!tc->misspeculating()) {
-            tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
-            tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
-                tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
-        }
+        tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
+        tc->setMiscRegNoEffect(IPR_IFAULT_VA_FORM,
+            tc->readMiscRegNoEffect(IPR_IVPTBR) | (VAddr(pc).vpn() << 3));
     }
 
     AlphaFault::invoke(tc);