1 files changed, 14 insertions, 12 deletions

diff --git a/src/arch/alpha/interrupts.hh b/src/arch/alpha/interrupts.hh
index a522dec6c..6453edf97 100644
--- a/src/arch/alpha/interrupts.hh
+++ b/src/arch/alpha/interrupts.hh
@@ -34,6 +34,7 @@
 
 #include "arch/alpha/faults.hh"
 #include "arch/alpha/isa_traits.hh"
+#include "base/compiler.hh"
 #include "cpu/thread_context.hh"
 
 namespace AlphaISA
@@ -52,11 +53,6 @@ namespace AlphaISA
             newInfoSet = false;
         }
 
-        void post(int int_type)
-        {
-            // sparc only
-        }
-
         void post(int int_num, int index)
         {
             DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
@@ -116,13 +112,13 @@ namespace AlphaISA
             int ipl = 0;
             int summary = 0;
 
-            if (tc->readMiscReg(IPR_ASTRR))
+            if (tc->readMiscRegNoEffect(IPR_ASTRR))
                 panic("asynchronous traps not implemented\n");
 
-            if (tc->readMiscReg(IPR_SIRR)) {
+            if (tc->readMiscRegNoEffect(IPR_SIRR)) {
                 for (int i = INTLEVEL_SOFTWARE_MIN;
                      i < INTLEVEL_SOFTWARE_MAX; i++) {
-                    if (tc->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+                    if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
                         // See table 4-19 of 21164 hardware reference
                         ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
                         summary |= (ULL(1) << i);
@@ -142,12 +138,12 @@ namespace AlphaISA
                 }
             }
 
-            if (ipl && ipl > tc->readMiscReg(IPR_IPLR)) {
+            if (ipl && ipl > tc->readMiscRegNoEffect(IPR_IPLR)) {
                 newIpl = ipl;
                 newSummary = summary;
                 newInfoSet = true;
                 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
-                        tc->readMiscReg(IPR_IPLR), ipl, summary);
+                        tc->readMiscRegNoEffect(IPR_IPLR), ipl, summary);
 
                 return new InterruptFault;
             } else {
@@ -158,11 +154,17 @@ namespace AlphaISA
         void updateIntrInfo(ThreadContext *tc)
         {
             assert(newInfoSet);
-            tc->setMiscReg(IPR_ISR, newSummary);
-            tc->setMiscReg(IPR_INTID, newIpl);
+            tc->setMiscRegNoEffect(IPR_ISR, newSummary);
+            tc->setMiscRegNoEffect(IPR_INTID, newIpl);
             newInfoSet = false;
         }
 
+        uint64_t get_vec(int int_num)
+        {
+            panic("Shouldn't be called for Alpha\n");
+            M5_DUMMY_RETURN
+        }
+
       private:
         bool newInfoSet;
         int newIpl;