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-rw-r--r--src/arch/alpha/isa.cc5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index 32d1aff65..685ddd479 100644
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -114,7 +114,7 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
}
void
-ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
+ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -140,8 +140,7 @@ ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
}
void
-ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
- ThreadID tid)
+ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR: