1 files changed, 15 insertions, 15 deletions

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index f41c46ac1..e6b4c234f 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -78,7 +78,7 @@ decode OPCODE default Unknown::unknown() {
                         uint64_t tmp = write_result;
                         // see stq_c
                         Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
-                    }}, mem_flags = LOCKED);
+                    }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
         0x2f: stq_c({{ Mem.uq = Ra; }},
                     {{
                         uint64_t tmp = write_result;
@@ -90,7 +90,7 @@ decode OPCODE default Unknown::unknown() {
                         // mailbox access, and we don't update the
                         // result register at all.
                         Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
-                    }}, mem_flags = LOCKED);
+                    }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
     }
 
     format IntegerOperate {
@@ -596,8 +596,8 @@ decode OPCODE default Unknown::unknown() {
             0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
             0x02f: fcmovgt({{ Fc = (Fa >  0) ? Fb : Fc; }});
 
-            0x024: mt_fpcr({{ FPCR = Fa.uq; }});
-            0x025: mf_fpcr({{ Fa.uq = FPCR; }});
+            0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
+            0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
         }
     }
 
@@ -628,7 +628,7 @@ decode OPCODE default Unknown::unknown() {
 #else
                 Ra = curTick;
 #endif
-            }});
+            }}, IsUnverifiable);
 
             // All of the barrier instructions below do nothing in
             // their execute() methods (hence the empty code blocks).
@@ -646,8 +646,8 @@ decode OPCODE default Unknown::unknown() {
             // a barrier on integer and FP traps.  "EXCB is thus a
             // superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
             // them the same though.
-            0x0000: trapb({{ }}, IsSerializing, No_OpClass);
-            0x0400: excb({{ }}, IsSerializing, No_OpClass);
+            0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
+            0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
             0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
             0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
         }
@@ -701,9 +701,9 @@ decode OPCODE default Unknown::unknown() {
                 xc->syscall(R0);
             }}, IsNonSpeculative);
             // Read uniq reg into ABI return value register (r0)
-            0x9e: rduniq({{ R0 = Runiq; }});
+            0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
             // Write uniq reg with value from ABI arg register (r16)
-            0x9f: wruniq({{ Runiq = R16; }});
+            0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
         }
     }
 #endif
@@ -740,7 +740,7 @@ decode OPCODE default Unknown::unknown() {
         format HwMoveIPR {
             1: hw_mfpr({{
                 Ra = xc->readMiscRegWithEffect(ipr_index, fault);
-            }});
+            }}, IsIprAccess);
         }
     }
 
@@ -750,14 +750,14 @@ decode OPCODE default Unknown::unknown() {
             1: hw_mtpr({{
                 xc->setMiscRegWithEffect(ipr_index, Ra);
                 if (traceData) { traceData->setData(Ra); }
-            }});
+            }}, IsIprAccess);
         }
     }
 
     format BasicOperate {
         0x1e: decode PALMODE {
             0: OpcdecFault::hw_rei();
-            1:hw_rei({{ xc->hwrei(); }}, IsSerializing);
+            1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
         }
 
         // M5 special opcodes use the reserved 0x01 opcode space
@@ -767,13 +767,13 @@ decode OPCODE default Unknown::unknown() {
             }}, IsNonSpeculative);
             0x01: quiesce({{
                 AlphaPseudo::quiesce(xc->xcBase());
-            }}, IsNonSpeculative);
+            }}, IsNonSpeculative, IsQuiesce);
             0x02: quiesceNs({{
                 AlphaPseudo::quiesceNs(xc->xcBase(), R16);
-            }}, IsNonSpeculative);
+            }}, IsNonSpeculative, IsQuiesce);
             0x03: quiesceCycles({{
                 AlphaPseudo::quiesceCycles(xc->xcBase(), R16);
-            }}, IsNonSpeculative);
+            }}, IsNonSpeculative, IsQuiesce);
             0x04: quiesceTime({{
                 R0 = AlphaPseudo::quiesceTime(xc->xcBase());
             }}, IsNonSpeculative);