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-rw-r--r--src/arch/alpha/isa/int.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/alpha/isa/int.isa b/src/arch/alpha/isa/int.isa
index bd9c3ccd9..265b3c4a9 100644
--- a/src/arch/alpha/isa/int.isa
+++ b/src/arch/alpha/isa/int.isa
@@ -110,7 +110,7 @@ def format IntegerOperate(code, *opt_flags) {{
# generate immediate version by substituting 'imm'
# note that imm takes no extenstion, so we extend
# the regexp to replace any extension as well
- imm_code = re.sub(r'Rb_or_imm(\.\w+)?', 'imm', orig_code)
+ imm_code = re.sub(r'Rb_or_imm(_\w+)?', 'imm', orig_code)
# generate declaration for register version
iop = InstObjParams(name, Name, 'AlphaStaticInst', code, opt_flags)