diff options
Diffstat (limited to 'src/arch/alpha/isa/mem.isa')
| -rw-r--r-- | src/arch/alpha/isa/mem.isa | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa index 0c8a404f0..3cdab6f47 100644 --- a/src/arch/alpha/isa/mem.isa +++ b/src/arch/alpha/isa/mem.isa @@ -51,8 +51,8 @@ output header {{ { } - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; /** @@ -88,8 +88,8 @@ output header {{ { } - std::string - generateDisassembly(Addr pc, const SymbolTable *symtab) const; + std::string generateDisassembly( + Addr pc, const SymbolTable *symtab) const override; }; }}; @@ -129,9 +129,10 @@ def template LoadStoreDeclare {{ /// Constructor. %(class_name)s(ExtMachInst machInst); - Fault execute(ExecContext *, Trace::InstRecord *) const; - Fault initiateAcc(ExecContext *, Trace::InstRecord *) const; - Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const; + Fault execute(ExecContext *, Trace::InstRecord *) const override; + Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override; + Fault completeAcc(PacketPtr, ExecContext *, + Trace::InstRecord *) const override; }; }}; |