2 files changed, 8 insertions, 8 deletions

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 49c25c3c2..b62372f66 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -638,7 +638,7 @@ decode OPCODE default Unknown::unknown() {
         /* Rb is a fake dependency so here is a fun way to get
          * the parser to understand that.
          */
-                Ra = xc->readMiscRegWithEffect(AlphaISA::IPR_CC) + (Rb & 0);
+                Ra = xc->readMiscReg(AlphaISA::IPR_CC) + (Rb & 0);
 
 #else
                 Ra = curTick;
@@ -690,7 +690,7 @@ decode OPCODE default Unknown::unknown() {
     0x00: CallPal::call_pal({{
         if (!palValid ||
             (palPriv
-             && xc->readMiscRegWithEffect(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) {
+             && xc->readMiscReg(AlphaISA::IPR_ICM) != AlphaISA::mode_kernel)) {
             // invalid pal function code, or attempt to do privileged
             // PAL call in non-kernel mode
             fault = new UnimplementedOpcodeFault;
@@ -701,8 +701,8 @@ decode OPCODE default Unknown::unknown() {
             bool dopal = xc->simPalCheck(palFunc);
 
             if (dopal) {
-                xc->setMiscRegWithEffect(AlphaISA::IPR_EXC_ADDR, NPC);
-                NPC = xc->readMiscRegWithEffect(AlphaISA::IPR_PAL_BASE) + palOffset;
+                xc->setMiscReg(AlphaISA::IPR_EXC_ADDR, NPC);
+                NPC = xc->readMiscReg(AlphaISA::IPR_PAL_BASE) + palOffset;
             }
         }
     }}, IsNonSpeculative);
@@ -760,7 +760,7 @@ decode OPCODE default Unknown::unknown() {
                     miscRegIndex >= NumInternalProcRegs)
                         fault = new UnimplementedOpcodeFault;
                 else
-                    Ra = xc->readMiscRegWithEffect(miscRegIndex);
+                    Ra = xc->readMiscReg(miscRegIndex);
             }}, IsIprAccess);
         }
     }
@@ -775,7 +775,7 @@ decode OPCODE default Unknown::unknown() {
                     miscRegIndex >= NumInternalProcRegs)
                         fault = new UnimplementedOpcodeFault;
                 else
-                    xc->setMiscRegWithEffect(miscRegIndex, Ra);
+                    xc->setMiscReg(miscRegIndex, Ra);
                 if (traceData) { traceData->setData(Ra); }
             }}, IsIprAccess);
         }
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index c845ea442..a350aa05f 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -46,7 +46,7 @@ output exec {{
     inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
         Fault fault = NoFault;	// dummy... this ipr access should not fault
-        if (!EV5::ICSR_FPE(xc->readMiscRegWithEffect(AlphaISA::IPR_ICSR))) {
+        if (!EV5::ICSR_FPE(xc->readMiscReg(AlphaISA::IPR_ICSR))) {
             fault = new FloatEnableFault;
         }
         return fault;
@@ -229,7 +229,7 @@ def template FloatingPointExecute {{
             %(code)s;
         } else {
             fesetround(getC99RoundingMode(
-                           xc->readMiscReg(AlphaISA::MISCREG_FPCR)));
+                           xc->readMiscRegNoEffect(AlphaISA::MISCREG_FPCR)));
             %(code)s;
             fesetround(FE_TONEAREST);
         }