summaryrefslogtreecommitdiff
path: root/src/arch/alpha/isa
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/alpha/isa')
-rw-r--r--src/arch/alpha/isa/branch.isa8
-rw-r--r--src/arch/alpha/isa/decoder.isa66
-rw-r--r--src/arch/alpha/isa/main.isa2
-rw-r--r--src/arch/alpha/isa/pal.isa6
4 files changed, 42 insertions, 40 deletions
diff --git a/src/arch/alpha/isa/branch.isa b/src/arch/alpha/isa/branch.isa
index aa7abf289..7438e7e18 100644
--- a/src/arch/alpha/isa/branch.isa
+++ b/src/arch/alpha/isa/branch.isa
@@ -106,7 +106,7 @@ output header {{
{
}
- Addr branchTarget(ExecContext *xc) const;
+ Addr branchTarget(ThreadContext *tc) const;
std::string
generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -121,10 +121,10 @@ output decoder {{
}
Addr
- Jump::branchTarget(ExecContext *xc) const
+ Jump::branchTarget(ThreadContext *tc) const
{
- Addr NPC = xc->readPC() + 4;
- uint64_t Rb = xc->readIntReg(_srcRegIdx[0]);
+ Addr NPC = tc->readPC() + 4;
+ uint64_t Rb = tc->readIntReg(_srcRegIdx[0]);
return (Rb & ~3) | (NPC & 1);
}
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 17132bbc2..fbdb119b6 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -80,7 +80,7 @@ decode OPCODE default Unknown::unknown() {
uint64_t tmp = write_result;
// see stq_c
Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
- }}, mem_flags = LOCKED);
+ }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
0x2f: stq_c({{ Mem.uq = Ra; }},
{{
uint64_t tmp = write_result;
@@ -92,7 +92,7 @@ decode OPCODE default Unknown::unknown() {
// mailbox access, and we don't update the
// result register at all.
Ra = (tmp == 0 || tmp == 1) ? tmp : Ra;
- }}, mem_flags = LOCKED);
+ }}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
}
format IntegerOperate {
@@ -598,8 +598,8 @@ decode OPCODE default Unknown::unknown() {
0x02e: fcmovle({{ Fc = (Fa <= 0) ? Fb : Fc; }});
0x02f: fcmovgt({{ Fc = (Fa > 0) ? Fb : Fc; }});
- 0x024: mt_fpcr({{ FPCR = Fa.uq; }});
- 0x025: mf_fpcr({{ Fa.uq = FPCR; }});
+ 0x024: mt_fpcr({{ FPCR = Fa.uq; }}, IsIprAccess);
+ 0x025: mf_fpcr({{ Fa.uq = FPCR; }}, IsIprAccess);
}
}
@@ -630,7 +630,7 @@ decode OPCODE default Unknown::unknown() {
#else
Ra = curTick;
#endif
- }});
+ }}, IsUnverifiable);
// All of the barrier instructions below do nothing in
// their execute() methods (hence the empty code blocks).
@@ -648,8 +648,8 @@ decode OPCODE default Unknown::unknown() {
// a barrier on integer and FP traps. "EXCB is thus a
// superset of TRAPB." (Alpha ARM, Sec 4.11.4) We treat
// them the same though.
- 0x0000: trapb({{ }}, IsSerializing, No_OpClass);
- 0x0400: excb({{ }}, IsSerializing, No_OpClass);
+ 0x0000: trapb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
+ 0x0400: excb({{ }}, IsSerializing, IsSerializeBefore, No_OpClass);
0x4000: mb({{ }}, IsMemBarrier, MemReadOp);
0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
}
@@ -703,9 +703,9 @@ decode OPCODE default Unknown::unknown() {
xc->syscall(R0);
}}, IsNonSpeculative);
// Read uniq reg into ABI return value register (r0)
- 0x9e: rduniq({{ R0 = Runiq; }});
+ 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess);
// Write uniq reg with value from ABI arg register (r16)
- 0x9f: wruniq({{ Runiq = R16; }});
+ 0x9f: wruniq({{ Runiq = R16; }}, IsIprAccess);
}
}
#endif
@@ -742,7 +742,7 @@ decode OPCODE default Unknown::unknown() {
format HwMoveIPR {
1: hw_mfpr({{
Ra = xc->readMiscRegWithEffect(ipr_index, fault);
- }});
+ }}, IsIprAccess);
}
}
@@ -752,69 +752,69 @@ decode OPCODE default Unknown::unknown() {
1: hw_mtpr({{
xc->setMiscRegWithEffect(ipr_index, Ra);
if (traceData) { traceData->setData(Ra); }
- }});
+ }}, IsIprAccess);
}
}
format BasicOperate {
0x1e: decode PALMODE {
0: OpcdecFault::hw_rei();
- 1:hw_rei({{ xc->hwrei(); }}, IsSerializing);
+ 1:hw_rei({{ xc->hwrei(); }}, IsSerializing, IsSerializeBefore);
}
// M5 special opcodes use the reserved 0x01 opcode space
0x01: decode M5FUNC {
0x00: arm({{
- AlphaPseudo::arm(xc->xcBase());
+ AlphaPseudo::arm(xc->tcBase());
}}, IsNonSpeculative);
0x01: quiesce({{
- AlphaPseudo::quiesce(xc->xcBase());
- }}, IsNonSpeculative);
+ AlphaPseudo::quiesce(xc->tcBase());
+ }}, IsNonSpeculative, IsQuiesce);
0x02: quiesceNs({{
- AlphaPseudo::quiesceNs(xc->xcBase(), R16);
- }}, IsNonSpeculative);
+ AlphaPseudo::quiesceNs(xc->tcBase(), R16);
+ }}, IsNonSpeculative, IsQuiesce);
0x03: quiesceCycles({{
- AlphaPseudo::quiesceCycles(xc->xcBase(), R16);
- }}, IsNonSpeculative);
+ AlphaPseudo::quiesceCycles(xc->tcBase(), R16);
+ }}, IsNonSpeculative, IsQuiesce);
0x04: quiesceTime({{
- R0 = AlphaPseudo::quiesceTime(xc->xcBase());
+ R0 = AlphaPseudo::quiesceTime(xc->tcBase());
}}, IsNonSpeculative);
0x10: ivlb({{
- AlphaPseudo::ivlb(xc->xcBase());
+ AlphaPseudo::ivlb(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
0x11: ivle({{
- AlphaPseudo::ivle(xc->xcBase());
+ AlphaPseudo::ivle(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
0x20: m5exit_old({{
- AlphaPseudo::m5exit_old(xc->xcBase());
+ AlphaPseudo::m5exit_old(xc->tcBase());
}}, No_OpClass, IsNonSpeculative);
0x21: m5exit({{
- AlphaPseudo::m5exit(xc->xcBase(), R16);
+ AlphaPseudo::m5exit(xc->tcBase(), R16);
}}, No_OpClass, IsNonSpeculative);
- 0x30: initparam({{ Ra = xc->xcBase()->getCpuPtr()->system->init_param; }});
+ 0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }});
0x40: resetstats({{
- AlphaPseudo::resetstats(xc->xcBase(), R16, R17);
+ AlphaPseudo::resetstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x41: dumpstats({{
- AlphaPseudo::dumpstats(xc->xcBase(), R16, R17);
+ AlphaPseudo::dumpstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x42: dumpresetstats({{
- AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17);
+ AlphaPseudo::dumpresetstats(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x43: m5checkpoint({{
- AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17);
+ AlphaPseudo::m5checkpoint(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x50: m5readfile({{
- R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18);
+ R0 = AlphaPseudo::readfile(xc->tcBase(), R16, R17, R18);
}}, IsNonSpeculative);
0x51: m5break({{
- AlphaPseudo::debugbreak(xc->xcBase());
+ AlphaPseudo::debugbreak(xc->tcBase());
}}, IsNonSpeculative);
0x52: m5switchcpu({{
- AlphaPseudo::switchcpu(xc->xcBase());
+ AlphaPseudo::switchcpu(xc->tcBase());
}}, IsNonSpeculative);
0x53: m5addsymbol({{
- AlphaPseudo::addsymbol(xc->xcBase(), R16, R17);
+ AlphaPseudo::addsymbol(xc->tcBase(), R16, R17);
}}, IsNonSpeculative);
0x54: m5panic({{
panic("M5 panic instruction called at pc=%#x.", xc->readPC());
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 91ece0935..1270bf8d8 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -56,7 +56,7 @@ output decoder {{
#include "base/fenv.hh"
#include "base/loader/symtab.hh"
#include "config/ss_compatible_fp.hh"
-#include "cpu/exec_context.hh" // for Jump::branchTarget()
+#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include <math.h>
diff --git a/src/arch/alpha/isa/pal.isa b/src/arch/alpha/isa/pal.isa
index 7c426a94e..f4c10da1d 100644
--- a/src/arch/alpha/isa/pal.isa
+++ b/src/arch/alpha/isa/pal.isa
@@ -266,9 +266,11 @@ output decoder {{
}
}};
-def format HwMoveIPR(code) {{
+def format HwMoveIPR(code, *flags) {{
+ all_flags = ['IprAccessOp']
+ all_flags += flags
iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code),
- ['IprAccessOp'])
+ all_flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 06:02:49 +0000