diff options
Diffstat (limited to 'src/arch/alpha/isa')
-rw-r--r-- | src/arch/alpha/isa/branch.isa | 40 | ||||
-rw-r--r-- | src/arch/alpha/isa/decoder.isa | 14 | ||||
-rw-r--r-- | src/arch/alpha/isa/main.isa | 9 |
3 files changed, 41 insertions, 22 deletions
diff --git a/src/arch/alpha/isa/branch.isa b/src/arch/alpha/isa/branch.isa index 974193efd..feb15b158 100644 --- a/src/arch/alpha/isa/branch.isa +++ b/src/arch/alpha/isa/branch.isa @@ -81,7 +81,7 @@ output header {{ { } - Addr branchTarget(Addr branchPC) const; + AlphaISA::PCState branchTarget(const AlphaISA::PCState &branchPC) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; @@ -106,7 +106,7 @@ output header {{ { } - Addr branchTarget(ThreadContext *tc) const; + AlphaISA::PCState branchTarget(ThreadContext *tc) const; std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; @@ -114,18 +114,19 @@ output header {{ }}; output decoder {{ - Addr - Branch::branchTarget(Addr branchPC) const + AlphaISA::PCState + Branch::branchTarget(const AlphaISA::PCState &branchPC) const { - return branchPC + 4 + disp; + return branchPC.pc() + 4 + disp; } - Addr + AlphaISA::PCState Jump::branchTarget(ThreadContext *tc) const { - Addr NPC = tc->readPC() + 4; + PCState pc = tc->pcState(); uint64_t Rb = tc->readIntReg(_srcRegIdx[0]); - return (Rb & ~3) | (NPC & 1); + pc.set((Rb & ~3) | (pc.pc() & 1)); + return pc; } const std::string & @@ -217,7 +218,14 @@ def template JumpOrBranchDecode {{ }}; def format CondBranch(code) {{ - code = 'bool cond;\n' + code + '\nif (cond) NPC = NPC + disp;\n'; + code = ''' + bool cond; + %(code)s; + PCState pc = PCS; + if (cond) + pc.npc(pc.npc() + disp); + PCS = pc; + ''' % { "code" : code } iop = InstObjParams(name, Name, 'Branch', code, ('IsDirectControl', 'IsCondControl')) header_output = BasicDeclare.subst(iop) @@ -229,16 +237,18 @@ def format CondBranch(code) {{ let {{ def UncondCtrlBase(name, Name, base_class, npc_expr, flags): # Declare basic control transfer w/o link (i.e. link reg is R31) - nolink_code = 'NPC = %s;\n' % npc_expr - nolink_iop = InstObjParams(name, Name, base_class, nolink_code, flags) + readpc_code = 'PCState pc = PCS;' + nolink_code = 'pc.npc(%s);\nPCS = pc' % npc_expr + nolink_iop = InstObjParams(name, Name, base_class, + readpc_code + nolink_code, flags) header_output = BasicDeclare.subst(nolink_iop) decoder_output = BasicConstructor.subst(nolink_iop) exec_output = BasicExecute.subst(nolink_iop) # Generate declaration of '*AndLink' version, append to decls - link_code = 'Ra = NPC & ~3;\n' + nolink_code + link_code = 'Ra = pc.npc() & ~3;\n' + nolink_code link_iop = InstObjParams(name, Name + 'AndLink', base_class, - link_code, flags) + readpc_code + link_code, flags) header_output += BasicDeclare.subst(link_iop) decoder_output += BasicConstructor.subst(link_iop) exec_output += BasicExecute.subst(link_iop) @@ -253,13 +263,13 @@ def UncondCtrlBase(name, Name, base_class, npc_expr, flags): def format UncondBranch(*flags) {{ flags += ('IsUncondControl', 'IsDirectControl') (header_output, decoder_output, decode_block, exec_output) = \ - UncondCtrlBase(name, Name, 'Branch', 'NPC + disp', flags) + UncondCtrlBase(name, Name, 'Branch', 'pc.npc() + disp', flags) }}; def format Jump(*flags) {{ flags += ('IsUncondControl', 'IsIndirectControl') (header_output, decoder_output, decode_block, exec_output) = \ - UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (NPC & 1)', flags) + UncondCtrlBase(name, Name, 'Jump', '(Rb & ~3) | (pc.npc() & 1)', flags) }}; diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index fe70e4d16..e2947cf4a 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -856,15 +856,16 @@ decode OPCODE default Unknown::unknown() { // invalid pal function code, or attempt to do privileged // PAL call in non-kernel mode fault = new UnimplementedOpcodeFault; - } - else { + } else { // check to see if simulator wants to do something special // on this PAL call (including maybe suppress it) bool dopal = xc->simPalCheck(palFunc); if (dopal) { - xc->setMiscReg(IPR_EXC_ADDR, NPC); - NPC = xc->readMiscReg(IPR_PAL_BASE) + palOffset; + PCState pc = PCS; + xc->setMiscReg(IPR_EXC_ADDR, pc.npc()); + pc.npc(xc->readMiscReg(IPR_PAL_BASE) + palOffset); + PCS = pc; } } }}, IsNonSpeculative); @@ -1030,13 +1031,14 @@ decode OPCODE default Unknown::unknown() { }}, IsNonSpeculative); #endif 0x54: m5panic({{ - panic("M5 panic instruction called at pc=%#x.", xc->readPC()); + panic("M5 panic instruction called at pc=%#x.", + xc->pcState().pc()); }}, IsNonSpeculative); #define CPANN(lbl) CPA::cpa()->lbl(xc->tcBase()) 0x55: decode RA { 0x00: m5a_old({{ panic("Deprecated M5 annotate instruction executed at pc=%#x\n", - xc->readPC()); + xc->pcState().pc()); }}, IsNonSpeculative); 0x01: m5a_bsm({{ CPANN(swSmBegin); diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa index 2a0699354..ffc267cd2 100644 --- a/src/arch/alpha/isa/main.isa +++ b/src/arch/alpha/isa/main.isa @@ -46,6 +46,7 @@ output header {{ #include <iomanip> #include "arch/alpha/faults.hh" +#include "arch/alpha/types.hh" #include "config/ss_compatible_fp.hh" #include "cpu/static_inst.hh" #include "mem/request.hh" // some constructors use MemReq flags @@ -185,7 +186,7 @@ def operands {{ 'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), 'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), 'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), - 'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), + 'PCS': ('PCState', 'uq', None, ( None, None, 'IsControl' ), 4), 'Runiq': ('ControlReg', 'uq', 'MISCREG_UNIQ', None, 1), 'FPCR': ('ControlReg', 'uq', 'MISCREG_FPCR', None, 1), 'IntrFlag': ('ControlReg', 'uq', 'MISCREG_INTR', None, 1), @@ -233,6 +234,12 @@ output header {{ std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; + + void + advancePC(AlphaISA::PCState &pcState) const + { + pcState.advance(); + } }; }}; |