summaryrefslogtreecommitdiff
path: root/src/arch/alpha/isa
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/alpha/isa')
-rw-r--r--src/arch/alpha/isa/fp.isa8
-rw-r--r--src/arch/alpha/isa/main.isa6
-rw-r--r--src/arch/alpha/isa/mem.isa37
-rw-r--r--src/arch/alpha/isa/opcdec.isa3
-rw-r--r--src/arch/alpha/isa/unimp.isa4
-rw-r--r--src/arch/alpha/isa/unknown.isa3
6 files changed, 27 insertions, 34 deletions
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index ea692aeef..36bfde2dd 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -42,7 +42,7 @@ output exec {{
/// instruction in full-system mode.
/// @retval Full-system mode: NoFault if FP is enabled, FenFault
/// if not. Non-full-system mode: always returns NoFault.
- inline Fault checkFpEnableFault(CPU_EXEC_CONTEXT *xc)
+ inline Fault checkFpEnableFault(ExecContext *xc)
{
Fault fault = NoFault; // dummy... this ipr access should not fault
if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
@@ -50,7 +50,7 @@ output exec {{
}
return fault;
}
- inline Fault checkVectorEnableFault(CPU_EXEC_CONTEXT *xc) {
+ inline Fault checkVectorEnableFault(ExecContext *xc) {
return std::make_shared<VectorEnableFault>();
}
}};
@@ -206,7 +206,7 @@ output decoder {{
// FP instruction class execute method template. Handles non-standard
// rounding modes.
def template FloatingPointExecute {{
- Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
if (trappingMode != Imprecise && !warnedOnTrapping) {
@@ -250,7 +250,7 @@ def template FloatingPointExecute {{
// rounding mode control is needed. Like BasicExecute, but includes
// check & warning for non-standard trapping mode.
def template FPFixedRoundingExecute {{
- Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
if (trappingMode != Imprecise && !warnedOnTrapping) {
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 34e2cb5ad..a6c9afe88 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -287,7 +287,7 @@ output decoder {{
// Declarations for execute() methods.
def template BasicExecDeclare {{
- Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+ Fault execute(ExecContext *, Trace::InstRecord *) const;
}};
// Basic instruction class declaration template.
@@ -316,7 +316,7 @@ def template BasicConstructor {{
// Basic instruction class execute method template.
def template BasicExecute {{
- Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -412,7 +412,7 @@ output decoder {{
output exec {{
Fault
- Nop::execute(CPU_EXEC_CONTEXT *, Trace::InstRecord *) const
+ Nop::execute(ExecContext *, Trace::InstRecord *) const
{
return NoFault;
}
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index 6ba8ee5d0..5c76c263e 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -141,17 +141,16 @@ def template LoadStoreDeclare {{
def template EACompDeclare {{
- Fault eaComp(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+ Fault eaComp(ExecContext *, Trace::InstRecord *) const;
}};
def template InitiateAccDeclare {{
- Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
}};
def template CompleteAccDeclare {{
- Fault completeAcc(PacketPtr, %(CPU_exec_context)s *,
- Trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
}};
def template LoadStoreConstructor {{
@@ -163,8 +162,8 @@ def template LoadStoreConstructor {{
}};
def template EACompExecute {{
- Fault %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
- Trace::InstRecord *traceData) const
+ Fault %(class_name)s::eaComp(ExecContext *xc,
+ Trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -185,7 +184,7 @@ def template EACompExecute {{
def template LoadExecute {{
- Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -211,7 +210,7 @@ def template LoadExecute {{
def template LoadInitiateAcc {{
- Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -232,8 +231,7 @@ def template LoadInitiateAcc {{
def template LoadCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt,
- CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -257,7 +255,7 @@ def template LoadCompleteAcc {{
def template StoreExecute {{
- Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -290,7 +288,7 @@ def template StoreExecute {{
}};
def template StoreCondExecute {{
- Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -324,7 +322,7 @@ def template StoreCondExecute {{
}};
def template StoreInitiateAcc {{
- Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -350,8 +348,7 @@ def template StoreInitiateAcc {{
def template StoreCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt,
- CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
{
return NoFault;
@@ -360,8 +357,7 @@ def template StoreCompleteAcc {{
def template StoreCondCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt,
- CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -385,7 +381,7 @@ def template StoreCondCompleteAcc {{
def template MiscExecute {{
- Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
Addr EA M5_VAR_USED;
@@ -408,7 +404,7 @@ def template MiscExecute {{
// Prefetches in Alpha don't actually do anything
// They just build an effective address and complete
def template MiscInitiateAcc {{
- Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::initiateAcc(ExecContext *xc,
Trace::InstRecord *traceData) const
{
warn("initiateAcc undefined: Misc instruction does not support split "
@@ -419,8 +415,7 @@ def template MiscInitiateAcc {{
def template MiscCompleteAcc {{
- Fault %(class_name)s::completeAcc(PacketPtr pkt,
- CPU_EXEC_CONTEXT *xc,
+ Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
Trace::InstRecord *traceData) const
{
warn("completeAcc undefined: Misc instruction does not support split "
diff --git a/src/arch/alpha/isa/opcdec.isa b/src/arch/alpha/isa/opcdec.isa
index ceb25cd96..3ea56573a 100644
--- a/src/arch/alpha/isa/opcdec.isa
+++ b/src/arch/alpha/isa/opcdec.isa
@@ -66,8 +66,7 @@ output decoder {{
output exec {{
Fault
- OpcdecFault::execute(CPU_EXEC_CONTEXT *xc,
- Trace::InstRecord *traceData) const
+ OpcdecFault::execute(ExecContext *xc, Trace::InstRecord *traceData) const
{
return std::make_shared<UnimplementedOpcodeFault>();
}
diff --git a/src/arch/alpha/isa/unimp.isa b/src/arch/alpha/isa/unimp.isa
index 26ec1c2bd..0446707bb 100644
--- a/src/arch/alpha/isa/unimp.isa
+++ b/src/arch/alpha/isa/unimp.isa
@@ -113,7 +113,7 @@ output decoder {{
output exec {{
Fault
- FailUnimplemented::execute(CPU_EXEC_CONTEXT *xc,
+ FailUnimplemented::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' "
@@ -122,7 +122,7 @@ output exec {{
}
Fault
- WarnUnimplemented::execute(CPU_EXEC_CONTEXT *xc,
+ WarnUnimplemented::execute(ExecContext *xc,
Trace::InstRecord *traceData) const
{
if (!warned) {
diff --git a/src/arch/alpha/isa/unknown.isa b/src/arch/alpha/isa/unknown.isa
index f356f24d8..7f5b9eb25 100644
--- a/src/arch/alpha/isa/unknown.isa
+++ b/src/arch/alpha/isa/unknown.isa
@@ -44,8 +44,7 @@ output decoder {{
output exec {{
Fault
- Unknown::execute(CPU_EXEC_CONTEXT *xc,
- Trace::InstRecord *traceData) const
+ Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
{
panic("attempt to execute unknown instruction "
"(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 05:12:15 +0000