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-rw-r--r--src/arch/alpha/isa/fp.isa6
-rw-r--r--src/arch/alpha/isa/main.isa4
-rw-r--r--src/arch/alpha/isa/mem.isa24
-rw-r--r--src/arch/alpha/isa/opcdec.isa2
-rw-r--r--src/arch/alpha/isa/unimp.isa4
-rw-r--r--src/arch/alpha/isa/unknown.isa2
6 files changed, 21 insertions, 21 deletions
diff --git a/src/arch/alpha/isa/fp.isa b/src/arch/alpha/isa/fp.isa
index e4b4c66c6..78a366ed2 100644
--- a/src/arch/alpha/isa/fp.isa
+++ b/src/arch/alpha/isa/fp.isa
@@ -42,7 +42,7 @@ output exec {{
/// instruction in full-system mode.
/// @retval Full-system mode: NoFault if FP is enabled, FenFault
/// if not. Non-full-system mode: always returns NoFault.
- inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+ inline Fault checkFpEnableFault(CPU_EXEC_CONTEXT *xc)
{
Fault fault = NoFault; // dummy... this ipr access should not fault
if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
@@ -203,7 +203,7 @@ output decoder {{
// FP instruction class execute method template. Handles non-standard
// rounding modes.
def template FloatingPointExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
if (trappingMode != Imprecise && !warnedOnTrapping) {
@@ -247,7 +247,7 @@ def template FloatingPointExecute {{
// rounding mode control is needed. Like BasicExecute, but includes
// check & warning for non-standard trapping mode.
def template FPFixedRoundingExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
if (trappingMode != Imprecise && !warnedOnTrapping) {
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index b2b35a1c1..a1d0de1d6 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -323,7 +323,7 @@ def template BasicConstructor {{
// Basic instruction class execute method template.
def template BasicExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -419,7 +419,7 @@ output decoder {{
output exec {{
Fault
- Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
+ Nop::execute(CPU_EXEC_CONTEXT *, Trace::InstRecord *) const
{
return NoFault;
}
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index 73b04c573..71b134340 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -163,7 +163,7 @@ def template LoadStoreConstructor {{
}};
def template EACompExecute {{
- Fault %(class_name)s::eaComp(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::eaComp(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -185,7 +185,7 @@ def template EACompExecute {{
def template LoadExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -211,7 +211,7 @@ def template LoadExecute {{
def template LoadInitiateAcc {{
- Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -233,7 +233,7 @@ def template LoadInitiateAcc {{
def template LoadCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr pkt,
- %(CPU_exec_context)s *xc,
+ CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -257,7 +257,7 @@ def template LoadCompleteAcc {{
def template StoreExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -290,7 +290,7 @@ def template StoreExecute {{
}};
def template StoreCondExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -324,7 +324,7 @@ def template StoreCondExecute {{
}};
def template StoreInitiateAcc {{
- Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Addr EA;
@@ -351,7 +351,7 @@ def template StoreInitiateAcc {{
def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr pkt,
- %(CPU_exec_context)s *xc,
+ CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
return NoFault;
@@ -361,7 +361,7 @@ def template StoreCompleteAcc {{
def template StoreCondCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr pkt,
- %(CPU_exec_context)s *xc,
+ CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -385,7 +385,7 @@ def template StoreCondCompleteAcc {{
def template MiscExecute {{
- Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
Addr EA M5_VAR_USED;
@@ -408,7 +408,7 @@ def template MiscExecute {{
// Prefetches in Alpha don't actually do anything
// They just build an effective address and complete
def template MiscInitiateAcc {{
- Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
+ Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
warn("initiateAcc undefined: Misc instruction does not support split "
@@ -420,7 +420,7 @@ def template MiscInitiateAcc {{
def template MiscCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr pkt,
- %(CPU_exec_context)s *xc,
+ CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
warn("completeAcc undefined: Misc instruction does not support split "
diff --git a/src/arch/alpha/isa/opcdec.isa b/src/arch/alpha/isa/opcdec.isa
index d279ae050..0051ea828 100644
--- a/src/arch/alpha/isa/opcdec.isa
+++ b/src/arch/alpha/isa/opcdec.isa
@@ -66,7 +66,7 @@ output decoder {{
output exec {{
Fault
- OpcdecFault::execute(%(CPU_exec_context)s *xc,
+ OpcdecFault::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
return new UnimplementedOpcodeFault;
diff --git a/src/arch/alpha/isa/unimp.isa b/src/arch/alpha/isa/unimp.isa
index 6cfaa6991..f9643d6b4 100644
--- a/src/arch/alpha/isa/unimp.isa
+++ b/src/arch/alpha/isa/unimp.isa
@@ -113,7 +113,7 @@ output decoder {{
output exec {{
Fault
- FailUnimplemented::execute(%(CPU_exec_context)s *xc,
+ FailUnimplemented::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' "
@@ -122,7 +122,7 @@ output exec {{
}
Fault
- WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
+ WarnUnimplemented::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
if (!warned) {
diff --git a/src/arch/alpha/isa/unknown.isa b/src/arch/alpha/isa/unknown.isa
index 1e95ccf68..b2e7d2d1b 100644
--- a/src/arch/alpha/isa/unknown.isa
+++ b/src/arch/alpha/isa/unknown.isa
@@ -44,7 +44,7 @@ output decoder {{
output exec {{
Fault
- Unknown::execute(%(CPU_exec_context)s *xc,
+ Unknown::execute(CPU_EXEC_CONTEXT *xc,
Trace::InstRecord *traceData) const
{
panic("attempt to execute unknown instruction "
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 03:00:19 +0000