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-rw-r--r--src/arch/alpha/isa/decoder.isa16
-rw-r--r--src/arch/alpha/isa/main.isa1
2 files changed, 15 insertions, 2 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 93b941d72..852f483e0 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -745,7 +745,13 @@ decode OPCODE default Unknown::unknown() {
0: OpcdecFault::hw_mfpr();
format HwMoveIPR {
1: hw_mfpr({{
- Ra = xc->readMiscRegWithEffect(ipr_index, fault);
+ int miscRegIndex = IprToMiscRegIndex[ipr_index];
+ if(miscRegIndex < 0 ||
+ (miscRegIndex >= MinWriteOnlyIpr &&
+ miscRegIndex <= MaxWriteOnlyIpr))
+ fault = new UnimplementedOpcodeFault;
+ else
+ Ra = xc->readMiscRegWithEffect(ipr_index, fault);
}}, IsIprAccess);
}
}
@@ -754,7 +760,13 @@ decode OPCODE default Unknown::unknown() {
0: OpcdecFault::hw_mtpr();
format HwMoveIPR {
1: hw_mtpr({{
- xc->setMiscRegWithEffect(ipr_index, Ra);
+ int miscRegIndex = IprToMiscRegIndex[ipr_index];
+ if(miscRegIndex < 0 ||
+ (miscRegIndex >= MinReadOnlyIpr &&
+ miscRegIndex <= MaxWriteOnlyIpr))
+ fault = new UnimplementedOpcodeFault;
+ else
+ xc->setMiscRegWithEffect(ipr_index, Ra);
if (traceData) { traceData->setData(Ra); }
}}, IsIprAccess);
}
diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 1df6ac603..06d3e8243 100644
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -71,6 +71,7 @@ output exec {{
#if FULL_SYSTEM
#include "sim/pseudo_inst.hh"
#endif
+#include "arch/alpha/ipr.hh"
#include "base/fenv.hh"
#include "config/ss_compatible_fp.hh"
#include "cpu/base.hh"