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-rw-r--r--src/arch/alpha/locked_mem.hh4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/alpha/locked_mem.hh b/src/arch/alpha/locked_mem.hh
index be5086bd7..56b5ba5ed 100644
--- a/src/arch/alpha/locked_mem.hh
+++ b/src/arch/alpha/locked_mem.hh
@@ -68,7 +68,7 @@ handleLockedWrite(XC *xc, Request *req)
if (req->isUncacheable()) {
// Funky Turbolaser mailbox access...don't update
// result register (see stq_c in decoder.isa)
- req->setScResult(2);
+ req->setExtraData(2);
} else {
// standard store conditional
bool lock_flag = xc->readMiscReg(MISCREG_LOCKFLAG);
@@ -76,7 +76,7 @@ handleLockedWrite(XC *xc, Request *req)
if (!lock_flag || (req->getPaddr() & ~0xf) != lock_addr) {
// Lock flag not set or addr mismatch in CPU;
// don't even bother sending to memory system
- req->setScResult(0);
+ req->setExtraData(0);
xc->setMiscReg(MISCREG_LOCKFLAG, false);
// the rest of this code is not architectural;
// it's just a debugging aid to help detect